diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-01-16 22:07:21 -0800 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-01-17 14:46:59 -0800 |
| commit | b9a322c2ca320c4a30a7991226a1646fc340e485 (patch) | |
| tree | caf0d48068734d88e6dfd407ccf6211246ad03d4 /arch/arm/mach-tegra/tegra_cl_dvfs.c | |
| parent | 5bf5a77113c0451e1cc3036945babe0c00e4b3ad (diff) | |
ARM: tegra: dvfs: Set DFLL clock data in common code
Set CL-DVFS data for DFLL target clock by CL-DVFS driver probe code
(instead of per-chip DFLL clock initialization).
Change-Id: I742093570245f6ef97dfdc908c538de6ff4c338e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/356964
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index fec1e443e366..bb9000475271 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -1481,6 +1481,8 @@ static int cl_dvfs_init(struct tegra_cl_dvfs *cld) cl_dvfs_init_cntrl_logic(cld); cl_dvfs_disable_clocks(cld); + /* Set target clock cl_dvfs data */ + clk_set_cl_dvfs_data(cld->dfll_clk, cld); return 0; } |