ARM: tegra: Move common timer code into timer.c

The system timer initialization code for Tegra2 and Tegra3 is
essentially the same except for the actual physical timer used and the
range of possible reference clock frequencies. This change removes the
needless duplication of code and restructures the system timer code into
common and SOC-specific parts.

Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15

1 files changed, 38 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/timer.h b/arch/arm/mach-tegra/timer.h
new file mode 100644
index 000000000000..03997517e155
--- /dev/null
+++ b/arch/arm/mach-tegra/timer.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-tegra/timer.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_TIMER_H_
+#define _MACH_TEGRA_TIMER_H_
+
+#define RTC_SECONDS		0x08
+#define RTC_SHADOW_SECONDS	0x0c
+#define RTC_MILLISECONDS	0x10
+
+#define TIMER_PTV		0x0
+#define TIMER_PCR		0x4
+
+#define TIMERUS_CNTR_1US	0x10
+#define TIMERUS_USEC_CFG	0x14
+#define TIMERUS_CNTR_FREEZE	0x4c
+
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra2_init_timer(u32 *offset, int *irq);
+#else
+void __init tegra3_init_timer(u32 *offset, int *irq);
+#endif
+
+#endif /* _MACH_TEGRA_TIMER_H_ */