diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-12-14 15:28:44 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 00:58:58 -0700 |
| commit | 5b8a516bea3a2b14599766ce968a5382b7c8cc8e (patch) | |
| tree | 67b518b38158ae5eb2979896d9f84748ccd85b2e /arch/arm/mach-tegra | |
| parent | f58c4d3f479f3247fc6f414b137d642e5a59b52d (diff) | |
ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limits
Added alternative frequency limits for Tegra3 CPU. These limits are
applied only in the lowest CPU EDP temperature zone, and the offset
from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling
voltage steps. Offset values as well as temperature threshold are to
be updated per characterization.
Bug 913884
Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/75615
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Rebase-Id: R407cbe270b2e10bc398c7f84840682f94c65c672
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/cpu-tegra.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/dvfs.h | 4 |
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index 96179f037948..d9b065231b49 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -38,6 +38,7 @@ #include "clock.h" #include "cpu-tegra.h" +#include "dvfs.h" /* tegra throttling and edp governors require frequencies in the table to be in ascending order */ @@ -223,11 +224,14 @@ int tegra_edp_update_thermal_zone(int temperature) mutex_lock(&tegra_cpu_lock); edp_thermal_index = index; - /* Update cpu rate if cpufreq (at least on cpu0) is already started */ + /* Update cpu rate if cpufreq (at least on cpu0) is already started; + alter cpu dvfs table for this thermal zone if necessary */ + tegra_cpu_dvfs_alter(edp_thermal_index, true); if (target_cpu_speed[0]) { edp_update_limit(); tegra_cpu_set_speed_cap(NULL); } + tegra_cpu_dvfs_alter(edp_thermal_index, false); mutex_unlock(&tegra_cpu_lock); return ret; diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 6fd581d7ded9..9a7552c9fbaf 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -124,6 +124,7 @@ int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate); void tegra_dvfs_core_cap_enable(bool enable); void tegra_dvfs_core_cap_level_set(int level); int tegra_dvfs_alt_freqs_set(struct dvfs *d, bool enable); +void tegra_cpu_dvfs_alter(int edp_thermal_index, bool before_clk_update); #else static inline int tegra_enable_dvfs_on_clk(struct clk *c, struct dvfs *d) { return 0; } @@ -158,6 +159,9 @@ static inline void tegra_dvfs_core_cap_level_set(int level) {} static inline int tegra_dvfs_alt_freqs_set(struct dvfs *d, bool enable) { return 0; } +static inline void tegra_cpu_dvfs_alter(int edp_thermal_index, + bool before_clk_update) +{} #endif #ifndef CONFIG_ARCH_TEGRA_2x_SOC |