diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2013-05-23 14:21:51 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:15:51 -0700 |
| commit | c9350241a7f1d12ccc02f527125a28bcc89e2538 (patch) | |
| tree | 94a163bfdb04417ff30f5be8be444746dcee1080 /arch/arm/mach-tegra | |
| parent | 8f5b819aa377ef872e1e6f06c24bb1050694a18a (diff) | |
arm: tegra: soctherm: fix heavy throttling on GPU zone
Fixed initialization of GPU throttling in level2 thermal control regs.
Bug 1169070
Change-Id: I121449b20fb987f61c6142e3783cd924f19a5bd6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/232300
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/tegra11_soctherm.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/tegra11_soctherm.c b/arch/arm/mach-tegra/tegra11_soctherm.c index 5b20f59c20ea..83021e700320 100644 --- a/arch/arm/mach-tegra/tegra11_soctherm.c +++ b/arch/arm/mach-tegra/tegra11_soctherm.c @@ -72,10 +72,12 @@ static const int precision; /* default 0 -> low precision */ #define CTL_LVL0_CPU0_DN_THRESH_MASK 0xff #define CTL_LVL0_CPU0_EN_SHIFT 8 #define CTL_LVL0_CPU0_EN_MASK 0x1 +#define CTL_LVL0_CPU0_DEV_THROT_LIGHT 0x1 +#define CTL_LVL0_CPU0_DEV_THROT_HEAVY 0x2 #define CTL_LVL0_CPU0_CPU_THROT_SHIFT 5 #define CTL_LVL0_CPU0_CPU_THROT_MASK 0x3 -#define CTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1 -#define CTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2 +#define CTL_LVL0_CPU0_GPU_THROT_SHIFT 3 +#define CTL_LVL0_CPU0_GPU_THROT_MASK 0x3 #define CTL_LVL0_CPU0_MEM_THROT_SHIFT 2 #define CTL_LVL0_CPU0_MEM_THROT_MASK 0x1 #define CTL_LVL0_CPU0_STATUS_SHIFT 0 @@ -660,13 +662,16 @@ static inline void prog_hw_threshold(struct thermal_trip_info *trip_state, r = soctherm_readl(reg_off); r = REG_SET(r, CTL_LVL0_CPU0_UP_THRESH, trip_temp); - r = REG_SET(r, CTL_LVL0_CPU0_DN_THRESH, trip_temp); r = REG_SET(r, CTL_LVL0_CPU0_EN, 1); r = REG_SET(r, CTL_LVL0_CPU0_CPU_THROT, throt == THROTTLE_HEAVY ? - CTL_LVL0_CPU0_CPU_THROT_HEAVY : - CTL_LVL0_CPU0_CPU_THROT_LIGHT); + CTL_LVL0_CPU0_DEV_THROT_HEAVY : + CTL_LVL0_CPU0_DEV_THROT_LIGHT); + r = REG_SET(r, CTL_LVL0_CPU0_GPU_THROT, + throt == THROTTLE_HEAVY ? + CTL_LVL0_CPU0_DEV_THROT_HEAVY : + CTL_LVL0_CPU0_DEV_THROT_LIGHT); soctherm_writel(r, reg_off); } @@ -2264,10 +2269,16 @@ static int regs_show(struct seq_file *s, void *data) state = REG_GET(r, CTL_LVL0_CPU0_EN); seq_printf(s, "En(%d) ", state); state = REG_GET(r, CTL_LVL0_CPU0_CPU_THROT); - seq_printf(s, "Throt"); + seq_printf(s, "Throt-CPU"); + seq_printf(s, "(%s) ", state ? + state == CTL_LVL0_CPU0_DEV_THROT_LIGHT ? "L" : + state == CTL_LVL0_CPU0_DEV_THROT_HEAVY ? "H" : + "H+L" : "none"); + state = REG_GET(r, CTL_LVL0_CPU0_GPU_THROT); + seq_printf(s, "Throt-GPU"); seq_printf(s, "(%s) ", state ? - state == CTL_LVL0_CPU0_CPU_THROT_LIGHT ? "L" : - state == CTL_LVL0_CPU0_CPU_THROT_HEAVY ? "H" : + state == CTL_LVL0_CPU0_DEV_THROT_LIGHT ? "L" : + state == CTL_LVL0_CPU0_DEV_THROT_HEAVY ? "H" : "H+L" : "none"); state = REG_GET(r, CTL_LVL0_CPU0_STATUS); seq_printf(s, "Status(%s)\n", |