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authorJay Agarwal <jagarwal@nvidia.com>2012-03-09 17:51:02 +0530
committerVarun Wadekar <vwadekar@nvidia.com>2012-04-11 12:21:05 +0530
commitdc0213a31f5c56fcce9ba99f9604cf5095945413 (patch)
tree14bc4581e460207fc942176575f8b2fe312fc393 /arch/arm/mach-tegra
parentd54b7368149690ba9dfe5da144ab35ebca890f85 (diff)
tegra:pcie: Correct pcie check link sequence
1. Removed mdelay in reset code since pci devices are not detected with this. 2. Moved the reset logic down in retry label. Bug 637871 Change-Id: Idd6344860e513407d5f8c8ba05e1beef0f39bf57 Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Reviewed-on: http://git-master/r/89128 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/pcie.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d929922f1c51..344ace587553 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -1099,13 +1099,6 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
int timeout;
do {
- /* Pulse the PEX reset */
- reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
- afi_writel(reg, reset_reg);
- mdelay(1);
- reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
- afi_writel(reg, reset_reg);
-
timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
while (timeout) {
reg = readl(pp->base + RP_VEND_XP);
@@ -1134,6 +1127,12 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
}
retry:
+ /* Pulse the PEX reset */
+ reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
+ afi_writel(reg, reset_reg);
+ reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
+ afi_writel(reg, reset_reg);
+
retries--;
} while (retries);