ARM: T132: dvfs: Update cldvfs table v4

Add PLLX based table for A01 and
CLDVFS based table for A02

Change-Id: Ibbec5b5d0dc9b43f6e4447791675a7226c732419
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/375803
Reviewed-by: Chao Xu <cxu@nvidia.com>

2 files changed, 36 insertions, 25 deletions

diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index f092cf9d7a62..f25064bf7d91 100644
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -30,6 +30,7 @@
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
 #include <linux/tegra-soc.h>
+#include <linux/tegra-fuse.h>
 
 #include <asm/clkdev.h>
 
@@ -4316,8 +4317,13 @@ static void __init tegra12_dfll_cpu_late_init(struct clk *c)
 	ret = tegra_init_cl_dvfs();
 	if (!ret) {
 		c->state = OFF;
-		if (tegra_platform_is_silicon())
+		if (tegra_platform_is_silicon()) {
 			use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
+#ifdef CONFIG_ARCH_TEGRA_13x_SOC
+			if (tegra_cpu_speedo_id() == 0)
+				use_dfll = 0;
+#endif
+		}
 		tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
 		tegra_cl_dvfs_debug_init(c);
 		pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll);
diff --git a/arch/arm/mach-tegra/tegra13_dvfs.c b/arch/arm/mach-tegra/tegra13_dvfs.c
index cc5d5da8d487..25a31891102a 100644
--- a/arch/arm/mach-tegra/tegra13_dvfs.c
+++ b/arch/arm/mach-tegra/tegra13_dvfs.c
@@ -79,7 +79,7 @@ static struct tegra_cooling_device gpu_vts_cdev = {
 
 static struct dvfs_rail tegra13_dvfs_rail_vdd_cpu = {
 	.reg_id = "vdd_cpu",
-	.version = "p4_v2",
+	.version = "p4v4",
 	.max_millivolts = 1300,
 	.min_millivolts = 700,
 	.step = VDD_SAFE_STEP,
@@ -200,16 +200,14 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		.voltage_scale = 1000,
 		.cvb_table = {
 			/*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
-			{510000,        {1413914, -39055, 488}, {980000, 0, 0}},
-			{612000,        {1491617, -40975, 488}, {1020000, 0, 0}},
-			{714000,        {1571360, -42895, 488}, {1060000, 0, 0}},
-			{816000,        {1653143, -44815, 488}, {1100000, 0, 0}},
-			{918000,        {1736966, -46725, 488}, {1150000, 0, 0}},
-			{1020000,       {1822828, -48645, 488}, {1190000, 0, 0}},
-			{1122000,       {1910731, -50565, 488}, {1230000, 0, 0}},
-			{1224000,       {2000673, -52485, 488}, {1260000, 0, 0}},
-			{1326000,       {2092656, -54405, 488}, {1260000, 0, 0}},
-			{1428000,       {2186678, -56325, 488}, {1260000, 0, 0}},
+			{510000,        {1413914, -39055, 488}, {880000, 0, 0}},
+			{612000,        {1491617, -40975, 488}, {920000, 0, 0}},
+			{714000,        {1571360, -42895, 488}, {960000, 0, 0}},
+			{816000,        {1653143, -44815, 488}, {1000000, 0, 0}},
+			{918000,        {1736966, -46725, 488}, {1050000, 0, 0}},
+			{1020000,       {1822828, -48645, 488}, {1090000, 0, 0}},
+			{1122000,       {1910731, -50565, 488}, {1130000, 0, 0}},
+			{1224000,       {2000673, -52485, 488}, {1170000, 0, 0}},
 			{      0 , 	{      0,      0,   0}, {      0, 0, 0}},
 		},
 		.vmin_trips_table = { 20, 35, 55, 75, },
@@ -220,11 +218,11 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		.speedo_id = 1,
 		.process_id = -1,
 		.dfll_tune_data  = {
-			.tune0		= 0x00FF2FFF,
-			.tune0_high_mv	= 0x00FF40E5,
+			.tune0		= 0x00FF10AE,
+			.tune0_high_mv	= 0x00FF40AE,
 			.tune1		= 0x000000FF,
 			.droop_rate_min = 1000000,
-			.tune_high_min_millivolts = 960,
+			.tune_high_min_millivolts = 900,
 			.min_millivolts = 800,
 			.tune_high_margin_mv = 30,
 		},
@@ -234,16 +232,23 @@ static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = {
 		.voltage_scale = 1000,
 		.cvb_table = {
 			/*f       dfll: c0,     c1,   c2  pll:  c0,   c1,    c2 */
-			{510000,        {1413914, -39055, 488}, {980000, 0, 0}},
-			{612000,        {1491617, -40975, 488}, {1020000, 0, 0}},
-			{714000,        {1571360, -42895, 488}, {1060000, 0, 0}},
-			{816000,        {1653143, -44815, 488}, {1100000, 0, 0}},
-			{918000,        {1736966, -46725, 488}, {1150000, 0, 0}},
-			{1020000,       {1822828, -48645, 488}, {1190000, 0, 0}},
-			{1122000,       {1910731, -50565, 488}, {1230000, 0, 0}},
-			{1224000,       {2000673, -52485, 488}, {1260000, 0, 0}},
-			{1326000,       {2092656, -54405, 488}, {1260000, 0, 0}},
-			{1428000,       {2186678, -56325, 488}, {1260000, 0, 0}},
+			{510000,        {900000, 0, 0}, {980000, 0, 0}},
+			{612000,        {900000, 0, 0}, {1020000, 0, 0}},
+			{714000,        {900000, 0, 0}, {1060000, 0, 0}},
+			{816000,        {900000, 0, 0}, {1100000, 0, 0}},
+			{918000,        {900000, 0, 0}, {1150000, 0, 0}},
+			{1020000,       {900000, 0, 0}, {1190000, 0, 0}},
+			{1122000,       {900000, 0, 0}, {1230000, 0, 0}},
+			{1224000,       {900000, 0, 0}, {1260000, 0, 0}},
+			{1326000,       {900000, 0, 0}, {1260000, 0, 0}},
+			{1428000,       {900000, 0, 0}, {1260000, 0, 0}},
+			{1530000,       {900000, 0, 0}, {1260000, 0, 0}},
+			{1632000,       {900000, 0, 0}, {1260000, 0, 0}},
+			{1734000,       {1260000, 0, 0}, {1260000, 0, 0}},
+			{1836000,       {1260000, 0, 0}, {1260000, 0, 0}},
+			{1928000,       {1260000, 0, 0}, {1260000, 0, 0}},
+			{2014500,       {1260000, 0, 0}, {1260000, 0, 0}},
+			{2116500,       {1260000, 0, 0}, {1260000, 0, 0}},
 			{      0 , 	{      0,      0,   0}, {      0, 0, 0}},
 		},
 		.vmin_trips_table = { 20, 35, 55, 75, },