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authorAlex Frid <afrid@nvidia.com>2010-03-08 19:02:01 -0800
committerGary King <gking@nvidia.com>2010-03-09 14:36:34 -0800
commit538ca3af7d82ab1724f4fa5413fc656825ef777f (patch)
tree68bd8491a003bc6cbe678fdea65e3e0754f2ddcf /arch/arm/mach-tegra
parent054802118fce840effebc090cf0bf03b2d122d7e (diff)
Tegra RM: Fixed MIPI PLL power rail control.
Fixed MIPI PLL power rail control that was missed by CL 5598660. (transparent for Whistler/Harmony where MIPI PLL rail is combined with other always On PLLs). Change-Id: Ic2e86df28e05dcd66d6b45f435bed882cf8ee7b4 Reviewed-on: http://git-master/r/811 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index 36dd76c92086..21bd7b8b18fe 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -1367,8 +1367,7 @@ NvRmPrivAp15PllDPowerControl(
// On exit from display clock configuration turn off PLLD power
// if it is disabled
if ((*pMipiPllVddOn) &&
- (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0) <=
- NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM)))
+ (NvRmPrivGetClockSourceFreq(NvRmClockSource_PllD0) == 0))
{
NvRmPrivPmuRailControl(hRmDevice, NV_VDD_PLLD_ODM_ID, NV_FALSE);
*pMipiPllVddOn = NV_FALSE;