diff options
| author | Daniel Solomon <daniels@nvidia.com> | 2012-07-10 19:13:58 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-02 13:51:46 -0700 |
| commit | 175312dabe42c3dd0615cec1af86f33476fb094a (patch) | |
| tree | 38bd07645bcb448c8ce4ac12b0c405310231f86f /arch/arm/mach-tegra | |
| parent | b8118a5fa5b482228d0c2bc9df069ea74b871110 (diff) | |
ARM: tegra: fuse: add function to read chip IDDQ
Add a function to read the fuse IDDQ register on T3x.
Change-Id: I41fc3a1144f86793e88aa4680b01b61e6c705342
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/116119
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/fuse.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/fuse.h | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index a3f4b0efe057..5a9b47e20b17 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -62,6 +62,7 @@ #define NUM_TSENSOR_SPARE_BITS 28 /* tsensor calibration register */ #define FUSE_TSENSOR_CALIB_0 0x198 +#define FUSE_IDDQ_CALIB_0 0x118 #endif @@ -177,6 +178,13 @@ int tegra_fuse_get_tsensor_spare_bits(u32 *spare_bits) return 0; } EXPORT_SYMBOL(tegra_fuse_get_tsensor_spare_bits); + +int tegra_fuse_get_cpu_iddq_mA(u32 *iddq) +{ + *iddq = tegra_fuse_readl(FUSE_IDDQ_CALIB_0); + *iddq = ((*iddq >> 5) & 0x3ff) * 8; + return 0; +} #endif unsigned long long tegra_chip_uid(void) diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index 262113087f60..2e12d91854e0 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -57,11 +57,13 @@ int tegra_cpu_speedo_id(void); int tegra_cpu_speedo_mv(void); int tegra_core_speedo_mv(void); int tegra_get_sku_override(void); +int tegra_fuse_get_cpu_iddq_mA(u32 *iddq); #else static inline int tegra_package_id(void) { return -1; } static inline int tegra_cpu_speedo_id(void) { return 0; } static inline int tegra_cpu_speedo_mv(void) { return 1000; } static inline int tegra_core_speedo_mv(void) { return 1200; } +static inline int tegra_fuse_get_cpu_iddq_mA(u32 *iddq) { return 0; } #endif /* CONFIG_ARCH_TEGRA_2x_SOC */ #else |