diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2011-04-15 16:01:00 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:56:01 -0700 |
| commit | 8e3dcaea5a7be65f50f9c1b8f07f38e8fd15b0e2 (patch) | |
| tree | fdb03b20ae48a2c36c0e72d3d8cc0569499faecc /arch/arm/mach-tegra | |
| parent | cf541b3005c38410fec58efe9623e97691f46b70 (diff) | |
dma: tegra: Resetting apb dma during kernel init
Resetting the apb dma controller and enabling the clock of the
apb dma controller during kernel initialization.
Making necessarily entry for the apb dma clock in clock table.
Original-Change-Id: Ifaed5a70ed06b162a5015a2eae8bb444b43178c4
Reviewed-on: http://git-master/r/27873
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Change-Id: If66c96a5e9cd015086f4d407ed9fc9bd99b6b29f
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/dma.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 2 |
3 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c index d80b02398fa4..e534c1867e76 100644 --- a/arch/arm/mach-tegra/dma.c +++ b/arch/arm/mach-tegra/dma.c @@ -27,10 +27,12 @@ #include <linux/err.h> #include <linux/irq.h> #include <linux/delay.h> +#include <linux/clk.h> #include <mach/dma.h> #include <mach/irqs.h> #include <mach/iomap.h> #include <mach/suspend.h> +#include <mach/clk.h> #define APB_DMA_GEN 0x000 #define GEN_ENABLE (1<<31) @@ -105,6 +107,7 @@ #define TEGRA_SYSTEM_DMA_CH_MAX \ (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1) +static struct clk *dma_clk; const unsigned int ahb_addr_wrap_table[8] = { 0, 32, 64, 128, 256, 512, 1024, 2048 }; @@ -877,6 +880,15 @@ int __init tegra_dma_init(void) unsigned int irq; void __iomem *addr; + dma_clk = clk_get_sys("apbdma", "apbdma"); + if (!IS_ERR_OR_NULL(dma_clk)) { + clk_enable(dma_clk); + tegra_periph_reset_assert(dma_clk); + udelay(10); + tegra_periph_reset_deassert(dma_clk); + udelay(10); + } + addr = IO_ADDRESS(TEGRA_APB_DMA_BASE); writel(GEN_ENABLE, addr + APB_DMA_GEN); writel(0, addr + APB_DMA_CNTRL); diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index a161cf42eaf8..845e91320ce2 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2009,6 +2009,7 @@ static struct clk tegra_clk_emc = { } struct clk tegra_list_clks[] = { + PERIPH_CLK("apbdma", "apbdma", "apbdma", 34, 0, 0x31E, 26000000, mux_clk_m, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("timer", "timer", NULL, 5, 0, 0x31E, 26000000, mux_clk_m, 0), diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 613bcaf8ab00..833dcb62fcb5 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3202,8 +3202,8 @@ static struct clk tegra_clk_emc = { .ops = &tegra_clk_shared_bus_ops, \ .parent = _parent, \ } - struct clk tegra_list_clks[] = { + PERIPH_CLK("apbdma", "apbdma", "apbdma", 34, 0, 26000000, mux_clk_m, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), |