diff options
| author | Kaz Fukuoka <kfukuoka@nvidia.com> | 2011-05-25 18:21:32 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2011-06-15 22:22:52 -0700 |
| commit | 5627dad2ca7b7196cb93025f0f44ffbeece8e9b7 (patch) | |
| tree | 721aea229e9e953dbbfc0583f315082f51eedc9b /arch/arm/mach-tegra | |
| parent | d697392e32fa0c7f84a2bdb5554ffad6af5c8522 (diff) | |
media: tegra: avp: Clear interrupt registers when AVP starts
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
bug 827353
bug 826234
Change-Id: Ia45efe1d5f2c48d8d372a2442a614d52f1a766c0
Reviewed-on: http://git-master/r/33083
Reviewed-on: http://git-master/r/35357
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/legacy_irq.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/legacy_irq.c | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h index 3a2bfab9e54f..82d1a226fa1c 100644 --- a/arch/arm/mach-tegra/include/mach/legacy_irq.h +++ b/arch/arm/mach-tegra/include/mach/legacy_irq.h @@ -31,6 +31,7 @@ int tegra_legacy_irq_set_wake(int irq, int enable); void tegra_legacy_irq_set_lp1_wake_mask(void); void tegra_legacy_irq_restore_mask(void); void tegra_init_legacy_irq(void); +void tegra_init_legacy_irq_cop(void); void tegra_legacy_irq_suspend(void); void tegra_legacy_irq_resume(void); #endif diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c index 5a6197bacbb1..a768f3e8d45b 100644 --- a/arch/arm/mach-tegra/legacy_irq.c +++ b/arch/arm/mach-tegra/legacy_irq.c @@ -174,6 +174,17 @@ void tegra_init_legacy_irq(void) } } +void tegra_init_legacy_irq_cop(void) +{ + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_COP_IER_CLR); + writel(0, ictlr + ICTLR_COP_IEP_CLASS); + } +} + #ifdef CONFIG_PM static u32 cop_ier[NUM_ICTLRS]; static u32 cpu_ier[NUM_ICTLRS]; |