[ARM/tegra] suspend: remove literals from CPU save & restore code

use the ARMv7 movw and movt instructions to load literal values, rather
than allowing the compiler to silently generate literal sections all over
memory

since this code needs to be relocatable (may run with no MMU, may run
with MMU, may run in IRAM), the fewer literals, the better

Change-Id: I06c3e1b607649946273a9b8cb87008bbec3bc4ae

3 files changed, 36 insertions, 28 deletions

diff --git a/arch/arm/mach-tegra/cortex_a9_save.S b/arch/arm/mach-tegra/cortex_a9_save.S
index 9eab4bd550b0..791856e5e8db 100644
--- a/arch/arm/mach-tegra/cortex_a9_save.S
+++ b/arch/arm/mach-tegra/cortex_a9_save.S
@@ -482,7 +482,7 @@ __tear_down_master:
 	 * preserve the data in the L2, the control words (L2X0_CTRL,
 	 * L2X0_AUX_CTRL, etc.) need to be cleaned to L3 so that they
 	 * will be visible on reboot */
-	ldr	r0, =(TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT)
+	mov32	r0, (TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT)
 	add	r3, r8, #(CONTEXT_SIZE_WORDS*4)
 	bic	r8, r8, #0x1f
 	add	r3, r3, #0x1f
@@ -508,14 +508,16 @@ __tear_down_master:
 	 * LP0 / LP1 use physical address, since the MMU needs to be
 	 * disabled before putting SDRAM into self-refresh to avoid
 	 * memory access due to page table walks */
-	ldreq	r4, =(TEGRA_PMC_BASE-IO_APB_PHYS+IO_APB_VIRT)
-	ldreq	r5, =(TEGRA_CLK_RESET_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
-	ldreq	r6, =(TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
-	ldreq	r7, =(TEGRA_TMRUS_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
-	ldrne	r4, =(TEGRA_PMC_BASE)
-	ldrne	r5, =(TEGRA_CLK_RESET_BASE)
-	ldrne	r6, =(TEGRA_FLOW_CTRL_BASE)
-	ldrne	r7, =(TEGRA_TMRUS_BASE)
+	mov32	r0, (IO_APB_VIRT-IO_APB_PHYS)
+	mov32	r4, TEGRA_PMC_BASE
+	addeq	r4, r4, r0
+	mov32	r0, (IO_PPSB_VIRT-IO_PPSB_PHYS)
+	mov32	r5, TEGRA_CLK_RESET_BASE
+	mov32	r6, TEGRA_FLOW_CTRL_BASE
+	mov32	r7, TEGRA_TMRUS_BASE
+	addeq	r5, r5, r0
+	addeq	r6, r6, r0
+	addeq	r7, r7, r0
 
 	beq	__tear_down_master_pll_cpu
 
@@ -530,7 +532,7 @@ __tear_down_master:
 	isb
 	mcr	p15, 0, r3, c2, c0, 0	@ TTB 0
 	isb
-	ldrne	r3, =(IO_IRAM_PHYS)	@ __tear_down_master_sdram, in IRAM
+	mov32	r3, (IO_IRAM_PHYS)	@ __tear_down_master_sdram, in IRAM
 	movne	pc, r3
 ENDPROC(__tear_down_master)
 	.type	__tear_down_master_data, %object
@@ -543,7 +545,7 @@ __tear_down_master_data:
 __tear_down_master_sdram:
 	mrc	p15, 0, r3, c1, c0, 0
 	bic	r3, r3, #(1<<0)
-	mcr	p15, 0, r3, c1, c0, 0	@ disable MMU
+	mcr	p15, 0, r3, c1, c0, 0	@ disable MMU to prevent page misses
 	/* FIXME: save off DDR pad settings, put SDRAM in self refresh,
 	 * jump to tear_down_master_pll_cpu */
 	b	.
@@ -625,14 +627,14 @@ __put_cpu_in_reset:
 	movne	r1, r1, lsl #3
 	addne	r1, r1, #0x14
 	moveq	r1, #0			@ r1 = CPUx_HALT_EVENTS register offset
-	ldr	r7, =(TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
+	mov32	r7, (TEGRA_FLOW_CTRL_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
 	mov	r2, #(0x2<<29)
 	str	r2, [r7, r1]		@ put flow controller in wait event mode
 	isb
 	dsb
-	ldr	r1, =0x1011
+	movw	r1, 0x1011
 	mov	r1, r1, lsl r0
-	ldr	r7, =(TEGRA_CLK_RESET_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
+	mov32	r7, (TEGRA_CLK_RESET_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT)
 	str	r1, [r7, #0x340]	@ put slave CPU in reset
 	isb
 	dsb
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 843b1108f386..d99404b67f5f 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -61,10 +61,10 @@ __invalidate_l1:
 	mcr	p15, 2, r0, c0, c0, 0
 	mrc	p15, 1, r0, c0, c0, 0
 
-	ldr	r1, =0x7fff
+	movw	r1, #0x7fff
 	and	r2, r1, r0, lsr #13
 
-	ldr	r1, =0x3ff
+	movw	r1, #0x3ff
 
 	and	r3, r1, r0, lsr #3  @ NumWays - 1
 	add	r2, r2, #1	@ NumSets
@@ -110,7 +110,7 @@ __invalidate_cpu_state:
 
 	cpu_id	r0
 	cmp	r0, #0
-	ldrne	r1, =(TEGRA_ARM_PERIF_BASE + 0xC)
+	mov32	r1, (TEGRA_ARM_PERIF_BASE + 0xC)
 	movne	r0, r0, lsl #2
 	movne	r2, #0xf
 	movne	r2, r2, lsl r0
@@ -159,14 +159,14 @@ __return_to_virtual:
 	mov	r0, #0x1f
 	mcr	p15, 0, r0, c3, c0, 0	@ domain access register
 
-	ldr	r0, =0xff0a81a8
-	ldr	r1, =0x40e040e0
+	mov32	r0, 0xff0a89a8
+	mov32	r1, 0x40e044e0
 	mcr	p15, 0, r0, c10, c2, 0	@ PRRR
 	mcr	p15, 0, r1, c10, c2, 1	@ NMRR
 	mrc	p15, 0, r0, c1, c0, 0
-	ldr	r1, =0x0120c302
+	mov32	r1, 0x0120c302
 	bic	r0, r0, r1
-	ldr	r1, =0x10c03c7d
+	mov32	r1, 0x10c03c7d
 	orr	r0, r0, r1
 
 #ifdef CONFIG_ALIGNMENT_TRAP
@@ -236,8 +236,8 @@ ENDPROC(__restart_pllx)
  */
 	.align L1_CACHE_SHIFT
 __enable_coresite_access:
-	ldr	r0, =(TEGRA_CLK_RESET_BASE + RST_DEVICES_U)
-	ldr	r2, =(TEGRA_TMRUS_BASE)
+	mov32	r0, (TEGRA_CLK_RESET_BASE + RST_DEVICES_U)
+	mov32	r2, (TEGRA_TMRUS_BASE)
 
 	/* assert reset for 2usec */
 	ldr	r1, [r0]
@@ -246,8 +246,8 @@ __enable_coresite_access:
 	wait_for_us r3, r2, r4
 	add	r3, r3, #2
 	bic	r1, r1, #(1<<9)
-	ldr	r5, =0xC5ACCE55
-	ldr	r6, =(TEGRA_CSITE_BASE + 0x10fb0)	@ CPUDBG0_LAR
+	mov32	r5, 0xC5ACCE55
+	mov32	r6, (TEGRA_CSITE_BASE + 0x10fb0)	@ CPUDBG0_LAR
 	mov	r7, #CONFIG_NR_CPUS
 	wait_until r3, r2, r4
 	str	r1, [r0]
@@ -268,9 +268,9 @@ ENDPROC(__enable_coresite_access)
 ENTRY(tegra_lp2_startup)
 	setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
 
-	ldr	r0, =TEGRA_TMRUS_BASE
+	mov32	r0, TEGRA_TMRUS_BASE
 	ldr	r1, [r0]
-	ldr	r0, =TEGRA_PMC_BASE
+	mov32	r0, TEGRA_PMC_BASE
 	str	r1, [r0, #PMC_SCRATCH39]	@ save off exact lp2 exit time
 	mov	r1, #0
 	str	r1, [r0, #PMC_DPD_SAMPLE]
@@ -284,7 +284,7 @@ ENTRY(tegra_lp2_startup)
 	mcr	p15, 0, r0, c1, c0, 1
 
 	/* enable SCU */
-	ldr	r0, =TEGRA_ARM_PERIF_BASE
+	mov32	r0, TEGRA_ARM_PERIF_BASE
 	ldr	r1, [r0]
 	orr	r1, r1, #1
 	str	r1, [r0]
diff --git a/arch/arm/mach-tegra/power-macros.S b/arch/arm/mach-tegra/power-macros.S
index 492416439760..9692de40bc6f 100644
--- a/arch/arm/mach-tegra/power-macros.S
+++ b/arch/arm/mach-tegra/power-macros.S
@@ -26,6 +26,12 @@
 	and	\rd, \rd, #0xF
 .endm
 
+
+.macro mov32, reg, val
+	movw	\reg, #:lower16:\val
+	movt	\reg, #:upper16:\val
+.endm
+
 /* waits until the microsecond counter (base) ticks, for exact timing loops */
 .macro	wait_for_us, rd, base, tmp
 	ldr	\rd, [\base]