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authorStefan Agner <stefan.agner@toradex.com>2014-01-13 12:32:29 +0100
committerStefan Agner <stefan.agner@toradex.com>2014-01-13 12:32:29 +0100
commit3d8f44c100f23574e9a4a9c74fa6054e48ca53c2 (patch)
tree8d19e521cf0c8daf3706a046547b15986f3b38da /arch/arm/mach-tegra
parentc54b9b8f76bfd8786c6cfbce942c1b1aebcb3ef1 (diff)
colibri_t20: video: use new modedb based settings
Use modedb to set mode on framebuffer/display controller for Tegra 20 based module Colibri T20 too.
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/board-colibri_t20-panel.c278
1 files changed, 21 insertions, 257 deletions
diff --git a/arch/arm/mach-tegra/board-colibri_t20-panel.c b/arch/arm/mach-tegra/board-colibri_t20-panel.c
index 6c6ff73eb318..8d8b9e74c58c 100644
--- a/arch/arm/mach-tegra/board-colibri_t20-panel.c
+++ b/arch/arm/mach-tegra/board-colibri_t20-panel.c
@@ -208,268 +208,13 @@ static struct resource colibri_t20_disp2_resources[] = {
},
};
-static struct tegra_dc_mode colibri_t20_panel_modes[] = {
-#ifdef TEGRA_FB_VGA
- {
- /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
- .pclk = 25175000, /* pixclock */
- .h_ref_to_sync = 8,
- .v_ref_to_sync = 2,
- .h_sync_width = 96, /* hsync_len */
- .v_sync_width = 2, /* vsync_len */
- .h_back_porch = 48, /* left_margin */
- .v_back_porch = 33, /* upper_margin */
- .h_active = 640,
- .v_active = 480,
- .h_front_porch = 16, /* right_margin */
- .v_front_porch = 10, /* lower_margin */
- },
-#else /* TEGRA_FB_VGA */
- {
- /* 800x480@60 (e.g. EDT ET070080DH6) */
- .pclk = 32460000,
- .h_ref_to_sync = 1,
- .v_ref_to_sync = 1,
- .h_sync_width = 64,
- .v_sync_width = 3,
- .h_back_porch = 128,
- .v_back_porch = 22,
- .h_active = 800,
- .v_active = 480,
- .h_front_porch = 64,
- .v_front_porch = 20,
- },
- {
- /* 800x600@60 */
- .pclk = 39272727,
- .h_sync_width = 80,
- .v_sync_width = 2,
- .h_back_porch = 160,
- .v_back_porch = 21,
- .h_active = 800,
- .v_active = 600,
- .h_front_porch = 16,
- .v_front_porch = 1,
- },
- {
- /* TouchRevolution Fusion 10 aka Chunghwa Picture Tubes
- CLAA101NC05 10.1 inch 1024x600 single channel LVDS panel */
- .pclk = 48000000,
- .h_sync_width = 5,
- .v_sync_width = 5,
- .h_back_porch = 104,
- .v_back_porch = 24,
- .h_active = 1024,
- .v_active = 600,
- .h_front_porch = 43,
- .v_front_porch = 20,
- },
- {
- /* 1024x768@60 */
-//pll_c 76Hz
- .pclk = 78800000,
- .h_sync_width = 96,
- .v_sync_width = 3,
- .h_back_porch = 176,
- .v_back_porch = 28,
- .h_active = 1024,
- .v_active = 768,
- .h_front_porch = 16,
- .v_front_porch = 1,
- },
- {
- /* 1024x768@75 */
- .pclk = 82000000,
- .h_sync_width = 104,
- .v_sync_width = 4,
- .h_back_porch = 168,
- .v_back_porch = 34,
- .h_active = 1024,
- .v_active = 768,
- .h_front_porch = 64,
- .v_front_porch = 3,
- },
- {
- /* 1280x720@70 */
- .pclk = 86400000,
- .h_ref_to_sync = 1,
- .v_ref_to_sync = 1,
- .h_sync_width = 40,
- .v_sync_width = 5,
- .h_back_porch = 220,
- .v_back_porch = 20,
- .h_active = 1280,
- .v_active = 720,
- .h_front_porch = 110,
- .v_front_porch = 5,
-//high active sync polarities
- },
- {
- /* 1280x1024@60 */
- .pclk = 108000000,
-// .h_ref_to_sync = 1,
-// .v_ref_to_sync = 1,
- .h_sync_width = 144,
- .v_sync_width = 3,
- .h_back_porch = 248,
- .v_back_porch = 38,
- .h_active = 1280,
- .v_active = 1024,
- .h_front_porch = 16,
- .v_front_porch = 1,
-//high active sync polarities
- },
- {
- /* 1366x768@60 */
- .pclk = 72072000,
- .h_ref_to_sync = 11,
- .v_ref_to_sync = 1,
- .h_sync_width = 58,
- .v_sync_width = 4,
- .h_back_porch = 58,
- .v_back_porch = 4,
- .h_active = 1366,
- .v_active = 768,
- .h_front_porch = 58,
- .v_front_porch = 4,
- },
- {
- /* 1600x1200@60 */
- .pclk = 144000000,
-//[ 1.423072] tegradc tegradc.0: can't divide 216000000 clock to 162000000 -1/+9% 144000000 160380000 176580000
-// .pclk = 162000000,
-// .h_ref_to_sync = 1,
-// .v_ref_to_sync = 1,
- .h_sync_width = 192,
- .v_sync_width = 3,
- .h_back_porch = 304,
- .v_back_porch = 46,
- .h_active = 1600,
- .v_active = 1200,
- .h_front_porch = 64,
- .v_front_porch = 1,
-//high active sync polarities
- },
- {
- /* 1680x1050@60 */
- .pclk = 144000000,
-//[ 1.423139] tegradc tegradc.0: can't divide 216000000 clock to 147140000 -1/+9% 144000000 145668600 160382600
-// .pclk = 147140000,
-// .h_ref_to_sync = 1,
-// .v_ref_to_sync = 1,
- .h_sync_width = 184,
- .v_sync_width = 3,
- .h_back_porch = 288,
- .v_back_porch = 33,
- .h_active = 1680,
- .v_active = 1050,
- .h_front_porch = 104,
- .v_front_porch = 1,
-//high active vertical sync polarity
- },
- {
- /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
- .pclk = 144000000,
-//[ 3.361002] tegradc tegradc.0: can't divide 216000000 clock to 148500000 -1/+9% 144000000 147015000 161865000
-// .pclk = 148500000,
- .h_ref_to_sync = 11,
- .v_ref_to_sync = 1,
- .h_sync_width = 44,
- .v_sync_width = 5,
- .h_back_porch = 148,
- .v_back_porch = 36,
- .h_active = 1920,
- .v_active = 1080,
- .h_front_porch = 88,
- .v_front_porch = 4,
-//high active sync polarities
- },
- {
- .pclk = 144000000,
-//[ 3.371657] tegradc tegradc.0: can't divide 216000000 clock to 154000000 -1/+9% 144000000 152460000 167860000
-// .pclk = 154000000,
- .h_ref_to_sync = 11,
- .v_ref_to_sync = 1,
- .h_sync_width = 32,
- .v_sync_width = 6,
- .h_back_porch = 80,
- .v_back_porch = 26,
- .h_active = 1920,
- .v_active = 1200,
- .h_front_porch = 48,
- .v_front_porch = 3,
- },
-
- /* portrait modes */
-
- {
- .pclk = 18000000,
- .h_ref_to_sync = 8,
- .v_ref_to_sync = 2,
- .h_sync_width = 4,
- .v_sync_width = 1,
- .h_back_porch = 20,
- .v_back_porch = 7,
- .h_active = 480,
- .v_active = 640,
- .h_front_porch = 8,
- .v_front_porch = 8,
- },
- {
- .pclk = 10000000,
- .h_ref_to_sync = 4,
- .v_ref_to_sync = 1,
- .h_sync_width = 16,
- .v_sync_width = 1,
- .h_back_porch = 32,
- .v_back_porch = 1,
- .h_active = 540,
- .v_active = 960,
- .h_front_porch = 32,
- .v_front_porch = 2,
- },
- {
- .pclk = 61417000,
- .h_ref_to_sync = 2,
- .v_ref_to_sync = 2,
- .h_sync_width = 4,
- .v_sync_width = 4,
- .h_back_porch = 100,
- .v_back_porch = 14,
- .h_active = 720,
- .v_active = 1280,
- .h_front_porch = 4,
- .v_front_porch = 4,
- },
-#endif /* TEGRA_FB_VGA */
-};
-
static struct tegra_fb_data colibri_t20_fb_data = {
.win = 0,
-#ifdef TEGRA_FB_VGA
- .xres = 640,
- .yres = 480,
-#else /* TEGRA_FB_VGA */
- .xres = 800,
- .yres = 480,
-#endif /* TEGRA_FB_VGA */
-#ifndef CONFIG_ANDROID
- .bits_per_pixel = 16,
-#else
- .bits_per_pixel = 32,
-#endif
.flags = TEGRA_FB_FLIP_ON_PROBE,
};
static struct tegra_fb_data colibri_t20_hdmi_fb_data = {
.win = 0,
- .xres = 640,
- .yres = 480,
-#ifndef CONFIG_ANDROID
- .bits_per_pixel = 16,
-#else
- .bits_per_pixel = 32,
-#endif
.flags = TEGRA_FB_FLIP_ON_PROBE,
};
@@ -499,8 +244,20 @@ static struct tegra_dc_out colibri_t20_disp1_out = {
.depth = 18,
.dither = TEGRA_DC_ORDERED_DITHER,
- .modes = colibri_t20_panel_modes,
- .n_modes = ARRAY_SIZE(colibri_t20_panel_modes),
+ /* Use 32-bit depth for android builds */
+#ifdef CONFIG_ANDROID
+#ifdef TEGRA_FB_VGA
+ .default_mode = "640x480-32@60",
+#else /* TEGRA_FB_VGA */
+ .default_mode = "800x480-32@60",
+#endif /* TEGRA_FB_VGA */
+#else /* CONFIG_ANDROID */
+#ifdef TEGRA_FB_VGA
+ .default_mode = "640x480-16@60",
+#else /* TEGRA_FB_VGA */
+ .default_mode = "800x480-16@60",
+#endif /* TEGRA_FB_VGA */
+#endif /* CONFIG_ANDROID */
.out_pins = colibri_t20_dc_out_pins,
.n_out_pins = ARRAY_SIZE(colibri_t20_dc_out_pins),
@@ -518,6 +275,13 @@ static struct tegra_dc_out colibri_t20_disp2_out = {
.max_pixclock = KHZ2PICOS(148500),
+ /* Use 32-bit depth for android builds */
+#ifdef CONFIG_ANDROID
+ .default_mode = "640x480-32@60",
+#else /* CONFIG_ANDROID */
+ .default_mode = "640x480-16@60",
+#endif /* CONFIG_ANDROID */
+
.align = TEGRA_DC_ALIGN_MSB,
.order = TEGRA_DC_ORDER_RED_BLUE,