diff options
| author | Nicolas Pitre <nico@cam.org> | 2009-03-27 14:22:26 -0400 |
|---|---|---|
| committer | Nicolas Pitre <nico@cam.org> | 2009-03-28 22:39:30 -0400 |
| commit | f000328ac10f23f4841b83ddc60eceb3ba0ac176 (patch) | |
| tree | bcd9597eb25e0285f3d9a61c6203e8ec92d8cdfb /arch/arm/mm/cache-feroceon-l2.c | |
| parent | d75de08727018659cd7e060cf0018eaf53e49aaf (diff) | |
[ARM] Kirkwood: small L2 code cleanup
Strictly speaking, a MCR instruction does not produce any output.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm/cache-feroceon-l2.c')
| -rw-r--r-- | arch/arm/mm/cache-feroceon-l2.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 1afed5068c2d..6e77c042d8e9 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -258,9 +258,7 @@ static void __init enable_dcache(void) static void __init __invalidate_icache(void) { - int dummy; - - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : "=r" (dummy)); + __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); } static int __init invalidate_and_disable_icache(void) |