diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2011-10-31 14:08:10 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-31 14:08:10 +0100 |
| commit | 08cab72f91c8b28ffabfd143119bccdd4a115ad7 (patch) | |
| tree | ccd5583971caecd82bf2d1e62691bf6e0362d650 /arch/arm/mm/proc-arm920.S | |
| parent | 86c1e5a74af11e4817ffa6d7748d9ac1353b5b53 (diff) | |
| parent | f37a53cc5d8a8fb199e41386d125d8c2ed9e54ef (diff) | |
Merge branch 'dt/gic' into next/dt
Conflicts:
arch/arm/include/asm/localtimer.h
arch/arm/mach-msm/board-msm8x60.c
arch/arm/mach-omap2/board-generic.c
Diffstat (limited to 'arch/arm/mm/proc-arm920.S')
| -rw-r--r-- | arch/arm/mm/proc-arm920.S | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 2e6849b41f66..88fb3d9e0640 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -379,31 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size -.equ cpu_arm920_suspend_size, 4 * 4 +.equ cpu_arm920_suspend_size, 4 * 3 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) - stmfd sp!, {r4 - r7, lr} + stmfd sp!, {r4 - r6, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c2, c0, 0 @ TTB address - mrc p15, 0, r7, c1, c0, 0 @ Control register - stmia r0, {r4 - r7} - ldmfd sp!, {r4 - r7, pc} + mrc p15, 0, r6, c1, c0, 0 @ Control register + stmia r0, {r4 - r6} + ldmfd sp!, {r4 - r6, pc} ENDPROC(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches - ldmia r0, {r4 - r7} + ldmia r0, {r4 - r6} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r6, c2, c0, 0 @ TTB address - mov r0, r7 @ control register - mov r2, r6, lsr #14 @ get TTB0 base - mov r2, r2, lsl #14 - ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ - PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE + mcr p15, 0, r1, c2, c0, 0 @ TTB address + mov r0, r6 @ control register b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif |