diff options
| author | Ingo Molnar <mingo@elte.hu> | 2010-01-13 09:58:37 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-01-13 10:08:50 +0100 |
| commit | 61405fea92c42d072d9b8bd189689f1502a838af (patch) | |
| tree | 013ea3e7ed71f4114004d5852d40b6e89e128f76 /arch/arm/mm/proc-arm946.S | |
| parent | 9c443dfdd31eddea6cbe6ee0ca469fbcc4e1dc3b (diff) | |
| parent | 1703f2c321a8a531c393e137a82602e16c6061cb (diff) | |
Merge branch 'perf/urgent' into perf/core
Merge reason: queue up dependent patch, update to -rc4
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mm/proc-arm946.S')
| -rw-r--r-- | arch/arm/mm/proc-arm946.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 40c0449a139b..9a951239c86c 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size * (same as arm926) */ -ENTRY(arm946_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(arm946_flush_kern_dcache_area) + add r1, r0, r1 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -280,7 +281,7 @@ ENTRY(arm946_cache_fns) .long arm946_flush_user_cache_range .long arm946_coherent_kern_range .long arm946_coherent_user_range - .long arm946_flush_kern_dcache_page + .long arm946_flush_kern_dcache_area .long arm946_dma_inv_range .long arm946_dma_clean_range .long arm946_dma_flush_range |