diff options
| author | Dave Jones <davej@redhat.com> | 2006-04-18 17:19:55 -0500 |
|---|---|---|
| committer | Dave Jones <davej@redhat.com> | 2006-04-18 17:19:55 -0500 |
| commit | f1f76afd71e0f17af9a35fcb649f4bab53304a4d (patch) | |
| tree | a56257b13a0eda4a9b7e950c3b85adad16341b80 /arch/arm/mm/proc-sa1100.S | |
| parent | 530515a06f90c0831732709efee4a99497bd2b7c (diff) | |
| parent | 385910f2b275a636238f70844f1b6da9fda6f2da (diff) | |
Merge ../linus
Diffstat (limited to 'arch/arm/mm/proc-sa1100.S')
| -rw-r--r-- | arch/arm/mm/proc-sa1100.S | 37 |
1 files changed, 5 insertions, 32 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 41f21f2dd8ff..777ad99c1439 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -30,30 +30,6 @@ * the cache line size of the I and D cache */ #define DCACHELINESIZE 32 -#define FLUSH_OFFSET 32768 - - .macro flush_1100_dcache rd, ra, re - ldr \rd, =flush_base - ldr \ra, [\rd] - eor \ra, \ra, #FLUSH_OFFSET - str \ra, [\rd] - add \re, \ra, #8192 @ only necessary for 8k -1001: ldr \rd, [\ra], #DCACHELINESIZE - teq \re, \ra - bne 1001b -#ifdef FLUSH_BASE_MINICACHE - add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE - add \re, \ra, #512 @ only 512 bytes -1002: ldr \rd, [\ra], #DCACHELINESIZE - teq \re, \ra - bne 1002b -#endif - .endm - - .data -flush_base: - .long FLUSH_BASE - .text __INIT @@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin) stmfd sp!, {lr} mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip - flush_1100_dcache r0, r1, r2 @ clean caches - mov r0, #0 - mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching + bl v4wb_flush_kern_cache_all + mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. @@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area) */ .align 5 ENTRY(cpu_sa1100_switch_mm) - flush_1100_dcache r3, ip, r1 - mov ip, #0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + str lr, [sp, #-4]! + bl v4wb_flush_kern_cache_all @ clears IP mcr p15, 0, ip, c9, c0, 0 @ invalidate RB - mcr p15, 0, ip, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs - mov pc, lr + ldr pc, [sp], #4 /* * cpu_sa1100_set_pte(ptep, pte) |