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| author | Tony Lindgren <tony@atomide.com> | 2011-09-22 16:38:39 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2011-09-22 16:38:39 -0700 |
| commit | 7a04c4cbf73953f1995a141534b7fe0c35828057 (patch) | |
| tree | 8b83a813600605510bd54cadb81f296d342e1b6b /arch/arm/mm/proc-v6.S | |
| parent | f8cf8e47fb87e3b27e63d36fc8d61b11273f37bc (diff) | |
| parent | fbe01f51a8260c1f0a66e8730c4fd2c5160ecb91 (diff) | |
Merge branch 'for_3.2/omap_device' of git://gitorious.org/khilman/linux-omap-pm into cleanup
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 219138d2f158..a923aa0fd00d 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -223,6 +223,22 @@ __v6_setup: mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them +#ifdef CONFIG_ARM_ERRATA_364296 + /* + * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data + * corruption with hit-under-miss enabled). The conditional code below + * (setting the undocumented bit 31 in the auxiliary control register + * and the FI bit in the control register) disables hit-under-miss + * without putting the processor into full low interrupt latency mode. + */ + ldr r6, =0x4107b362 @ id for ARM1136 r0p2 + mrc p15, 0, r5, c0, c0, 0 @ get processor id + teq r5, r6 @ check for the faulty core + mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg + orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + orreq r0, r0, #(1 << 21) @ low interrupt latency configuration +#endif mov pc, lr @ return to head.S:__ret /* |