diff options
author | Marc Zyngier <marc.zyngier@arm.com> | 2018-02-01 11:07:36 +0000 |
---|---|---|
committer | Winnie Hsu <whsu@nvidia.com> | 2018-04-28 23:30:54 -0700 |
commit | 9606849c487e3963e25a0cb632cbe44f8f0d5744 (patch) | |
tree | 556338e6105f5659fd844d934bd05efbb8903615 /arch/arm/mm/proc-v7-3level.S | |
parent | 94606f27e4dfd95cf4c83dba8b7356de91e2859d (diff) |
arm: Add icache invalidation on switch_mm for Cortex-A15
** Not yet queued for inclusion in mainline **
In order to avoid aliasing attacks against the branch predictor,
Cortex-A15 require to invalidate the BTB when switching
from one user context to another. The only way to do so on this
CPU is to perform an ICIALLU, having set ACTLR[0] to 1 from secure
mode.
Change-Id: Ib0083803d75a4399b8225193349a4b490d1776a1
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698398
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Diffstat (limited to 'arch/arm/mm/proc-v7-3level.S')
-rw-r--r-- | arch/arm/mm/proc-v7-3level.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index e377cc4031b0..8ba8dfd0531e 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -53,6 +53,15 @@ * Set the translation table base pointer to be pgd_phys (physical address of * the new TTB). */ +ENTRY(cpu_v7_icinv_switch_mm) +#ifdef CONFIG_MMU + /* + * Cortex-A15 requires ACTLR[0] to be set from secure in order + * for the icache invalidation to also invalidate the BTB. + */ + mcr p15, 0, r0, c7, c5, 0 @ ICIALLU + /* Fall through to switch_mm... */ +#endif ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mmid r2, r2 @ get mm->context.id @@ -64,6 +73,7 @@ ENTRY(cpu_v7_switch_mm) #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) +ENDPROC(cpu_v7_icinv_switch_mm) /* * cpu_v7_set_pte_ext(ptep, pte) |