diff options
| author | Xin Xie <xxie@nvidia.com> | 2011-04-12 19:37:55 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-25 15:56:47 -0700 |
| commit | 13d6b6cf06caba33ade36f132c603e721affcfaf (patch) | |
| tree | 528e2674a5a34ee8ac62ed5dab2ca2aa42c5ef24 /arch/arm/mm/proc-v7.S | |
| parent | e2a716d266285140c765cf12c8c820cfcfa8442b (diff) | |
ARM: mm: domain switch removal
This patch has 2 purposes:
* Disable CPU prefetching ioremap'ed memory
* Keep Copy-On-Write policy for some CPU instructions emulation in
kernel space(i.e. SWP)
This is the backport of the upstream Linux kernel:
* ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs
(main kernel commit ID: 247055aa21ffef1c49dd64710d5e94c2aee19b58)
Change-Id: Ic467be916282278e104192401b5289d283317f1a
Reviewed-on: http://git-master/r/29734
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 4494070855d2..247eeffd4353 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -149,8 +149,11 @@ ENTRY(cpu_v7_set_pte_ext) tst r1, #L_PTE_USER orrne r3, r3, #PTE_EXT_AP1 +#ifdef CONFIG_CPU_USE_DOMAINS + @ allow kernel read/write access to read-only user pages tstne r3, #PTE_EXT_APX bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 +#endif tst r1, #L_PTE_EXEC orreq r3, r3, #PTE_EXT_XN @@ -300,8 +303,6 @@ __v7_setup: mcr p15, 0, r10, c2, c0, 2 @ TTB control register orr r4, r4, #TTB_FLAGS mcr p15, 0, r4, c2, c0, 1 @ load TTB1 - mov r10, #0x1f @ domains 0, 1 = manager - mcr p15, 0, r10, c3, c0, 0 @ load domain access register /* * Memory region attributes with SCTLR.TRE=1 * |