diff options
| author | vdumpa <vdumpa@nvidia.com> | 2011-04-27 11:11:44 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-04-28 19:51:45 -0700 |
| commit | b501cafea7328bc578f67e3e846ab9d25b7ec1b0 (patch) | |
| tree | f9c73977c78dd11c7a6ff4ed02a0c0b88ec766b2 /arch/arm/mm | |
| parent | bc6cb0878899b3af84b1c4bede522dc6232052d7 (diff) | |
ARM: errata: 752520: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock.
Under rare circumstances, PLDs may interfere with a Cacheable page table walk,
creating a processor deadlock. The erratum can only happen when the Data Cache
and MMU are enabled, with the TLB descriptors marked as L1 cacheable,
so that Page Table Walks are performed as cache linefills.
This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing PLD operations treated as NOP.
Change-Id: Ic704a42e786db2843d718a6ed06e402f63eca387
Reviewed-on: http://git-master/r/29540
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 17cda88ceaa7..453e3fe0dd92 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -281,6 +281,12 @@ __v7_setup: orrlt r10, r10, #1 << 11 @ set bit #11 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_752520 + cmp r6, #0x29 @ present prior to r2p9 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 20 @ set bit #20 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 #ifdef HARVARD_CACHE |