[ARM] outer cache: add outer_cache sync function

memory shared with DMA devices which has been mapped bufferable
or outer-non-cacheable may be stored in a write buffer inside
the outer cache.

there was no exposed mechanism for flushing just these writebuffers
to memory (aside from abusing an outer cache maintenance operation
which implicitly performed the sync).

this change adds a sync callback to the outer_cache structure and
implements this callback for the ARM PL2x0 and PL3x0 cache controllers.

Change-Id: I6d9bd38a6f486044ade85f38bbbaba6960c4b714

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index be8eb432e17c..7a3270a5b3a6 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -98,6 +98,11 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	cache_sync();
 }
 
+static void l2x0_sync(void)
+{
+	cache_sync();
+}
+
 void l2x0_deinit()
 {
 	/* FIXME: get num_ways from the cache config */
@@ -164,6 +169,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 	outer_cache.inv_range = l2x0_inv_range;
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
+	outer_cache.sync = l2x0_sync;
 
 	printk(KERN_INFO "L2X0 cache controller enabled\n");
 }