diff options
| author | Ian Wisbon <ian.wisbon@timesys.com> | 2011-02-14 16:41:03 -0500 |
|---|---|---|
| committer | Ian Wisbon <ian.wisbon@timesys.com> | 2011-02-14 16:41:03 -0500 |
| commit | 8a83780a187ba1961380814eaf9c503043345d12 (patch) | |
| tree | 80f5d89cca49330e137688c72fb10c9f42dc5663 /arch/arm/plat-mxc/include/mach/mx5x.h | |
| parent | 14a4057959f8ee0a2249eb2abd64fd6b1f571d98 (diff) | |
Digi Release Code from del-5.6/main2.6.31-digi-201102141643
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx5x.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx5x.h | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h index 0e25133736d2..fd3bbefdd292 100644 --- a/arch/arm/plat-mxc/include/mach/mx5x.h +++ b/arch/arm/plat-mxc/include/mach/mx5x.h @@ -134,31 +134,6 @@ */ #define MX53_SATA_BASE_ADDR 0x10000000 -/* - * Databahn MX50 - */ -#define MX50_DATABAHN_BASE_ADDR 0x14000000 -#define DATABAHN_CTL_REG19 0x4c -#define DATABAHN_CTL_REG20 0x50 -#define DATABAHN_CTL_REG21 0x54 -#define DATABAHN_CTL_REG22 0x58 -#define DATABAHN_CTL_REG23 0x5c -#define DATABAHN_CTL_REG42 0xa8 -#define DATABAHN_CTL_REG43 0xac -#define DATABAHN_CTL_REG55 0xdc -#define DATABAHN_CTL_REG63 0xFC -#define LOWPOWER_CONTROL_MASK 0x1F -#define LOWPOWER_AUTOENABLE_MASK 0x1F -#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16) -#define LOWPOWER_EXTERNAL_CNT_OFFSET 16 -#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8) -#define LOWPOWER_INTERNAL_CNT_OFFSET 8 -#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16) -#define LOWPOWER_REFRESH_ENABLE_OFFSET 16 -#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF -#define LOWPOWER_REFRESH_HOLD_OFFSET 0 - - #define DEBUG_BASE_ADDR 0x40000000 /*MX53 + 0x2000000 */ #define DEBUG_SIZE SZ_1M @@ -171,7 +146,7 @@ #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) -#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) +#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) #define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) #define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) #define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) @@ -262,7 +237,6 @@ #define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) -#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */ #define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) #define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4) |