Linux 2.6.31 Release for Digi ConnectCore Wi-i.MX boards2.6.31-digi-201102101717

1 files changed, 89 insertions, 2 deletions

diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 5be0f426c7da..0e25133736d2 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -93,7 +93,7 @@
 #endif
 
 #ifdef CONFIG_MXC_VPU_IRAM
-#define VPU_IRAM_SIZE  0x11000
+#define VPU_IRAM_SIZE  0x14000
 #else
 #define VPU_IRAM_SIZE 0
 #endif
@@ -129,6 +129,36 @@
 #define MX51_TZIC_BASE_ADDR		0xE0000000
 #define TZIC_SIZE		SZ_16K
 
+/*
+ * AHCI SATA
+ */
+#define MX53_SATA_BASE_ADDR 		0x10000000
+
+/*
+ * Databahn MX50
+ */
+#define MX50_DATABAHN_BASE_ADDR		0x14000000
+#define DATABAHN_CTL_REG19			0x4c
+#define DATABAHN_CTL_REG20			0x50
+#define DATABAHN_CTL_REG21			0x54
+#define DATABAHN_CTL_REG22			0x58
+#define DATABAHN_CTL_REG23			0x5c
+#define DATABAHN_CTL_REG42			0xa8
+#define DATABAHN_CTL_REG43			0xac
+#define DATABAHN_CTL_REG55			0xdc
+#define DATABAHN_CTL_REG63			0xFC
+#define LOWPOWER_CONTROL_MASK	 	0x1F
+#define LOWPOWER_AUTOENABLE_MASK 		0x1F
+#define LOWPOWER_EXTERNAL_CNT_MASK		(0xFFFF << 16)
+#define LOWPOWER_EXTERNAL_CNT_OFFSET	16
+#define LOWPOWER_INTERNAL_CNT_MASK		(0xFFFF << 8)
+#define LOWPOWER_INTERNAL_CNT_OFFSET	8
+#define LOWPOWER_REFRESH_ENABLE_MASK	(3 << 16)
+#define LOWPOWER_REFRESH_ENABLE_OFFSET	16
+#define LOWPOWER_REFRESH_HOLD_MASK		0xFFFF
+#define LOWPOWER_REFRESH_HOLD_OFFSET	0
+
+
 #define DEBUG_BASE_ADDR	0x40000000
 /*MX53 + 0x2000000 */
 #define DEBUG_SIZE		SZ_1M
@@ -141,6 +171,22 @@
 #define CTI3_BASE_ADDR		(DEBUG_BASE_ADDR + 0x00007000)
 #define CORTEX_DBG_BASE_ADDR	(DEBUG_BASE_ADDR + 0x00008000)
 
+#define APBHDMA_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01000000)
+#define OCOTP_CTRL_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01002000)
+#define DIGCTL_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01004000)
+#define GPMI_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01006000)
+#define BCH_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01008000)
+#define ELCDIF_BASE_ADDR	(DEBUG_BASE_ADDR + 0x0100A000)
+#define EPXP_BASE_ADDR		(DEBUG_BASE_ADDR + 0x0100C000)
+#define DCP_BASE_ADDR		(DEBUG_BASE_ADDR + 0x0100E000)
+#define EPDC_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01010000)
+#define QOSC_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01012000)
+#define PERFMON_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01014000)
+#define SSP_BASE_ADDR		(DEBUG_BASE_ADDR + 0x01016000)
+#define ANATOP_BASE_ADDR	(DEBUG_BASE_ADDR + 0x01018000)
+
+#define MX50_NIC_BASE_ADDR	(DEBUG_BASE_ADDR + 0x08000000)
+
 /*
  * SPBA global module enabled #0
  */
@@ -216,6 +262,7 @@
 #define MX53_ATA_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000E8000)
 #define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
 #define UART4_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000F0000)
+#define RNGB_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */
 
 #define DVFSCORE_BASE_ADDR 	(GPC_BASE_ADDR + 0x180)
 #define DVFSPER_BASE_ADDR 		(GPC_BASE_ADDR + 0x1C4)
@@ -371,7 +418,7 @@
 #define NFC_AXI_IO_ADDRESS(x)  \
 	(((x) - NFC_BASE_ADDR_AXI) + NFC_BASE_ADDR_AXI_VIRT)
 
-#define MX53_BASE_ADDR(x) (cpu_is_mx53() ? (x) - 0x20000000 : (x))
+#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x))
 
 #define IS_MEM_DEVICE_NONSHARED(x)		0
 
@@ -388,6 +435,8 @@
 #define DMA_REQ_SLIM_B_TX				42 /* MX51 */
 #define DMA_REQ_UART3_TX_MX51		44
 #define DMA_REQ_UART3_RX_MX51		43
+#define DMA_REQ_UART3_TX_MX50		43
+#define DMA_REQ_UART3_RX_MX50		42
 #define DMA_REQ_ESAI_TX				41
 #define DMA_REQ_SDHC4_MX51			41
 #define DMA_REQ_ESAI_RX				40
@@ -434,9 +483,13 @@
 #define DMA_REQ_UART5_RX				16
 #define DMA_REQ_SPDIF_TX				15
 #define DMA_REQ_SPDIF_RX				14
+#define DMA_REQ_EXTREQ0_MX50				14
+#define DMA_REQ_EXTREQ1_MX50				15
 /* UART2 is shared w/FIRI on MX53 */
 #define DMA_REQ_FIRI_TX					13
 #define DMA_REQ_FIRI_RX				12
+#define DMA_REQ_UART2_TX_MX50				13
+#define DMA_REQ_UART2_RX_MX50				12
 #define DMA_REQ_SDHC4_MX53			11
 
 #define DMA_REQ_HS_I2C_RX				11 /* MX51 */
@@ -453,7 +506,9 @@
 #define DMA_REQ_SLIM_B					5 /* MX51 */
 #define DMA_REQ_ATA_TX_END			4
 #define DMA_REQ_ATA_TX					3
+#define DMA_REQ_UART4_TX_MX50				3
 #define DMA_REQ_ATA_RX					2
+#define DMA_REQ_UART4_RX_MX50				2
 #define DMA_REQ_GPC					1
 #define DMA_REQ_VPU					0
 
@@ -481,16 +536,21 @@
 #define MXC_INT_USB_H3		17
 #define MXC_INT_USB_OTG	18
 #define MXC_INT_SAHARA_H0	19
+#define MXC_INT_DATABAHN	19 /* MX50 */
 #define MXC_INT_SAHARA_H1	20
+#define MXC_INT_ELCDIF		20 /* MX50 */
 #define MXC_INT_SCC_SMN	21
+#define MXC_INT_EPXP		21 /* MX50 */
 #define MXC_INT_SCC_STZ	22
 #define MXC_INT_SCC_SCM	23
 #define MXC_INT_SRTC_NTZ	24
 #define MXC_INT_SRTC_TZ	25
 #define MXC_INT_RTIC		26
 #define MXC_INT_CSU		27
+#define MXC_INT_EPDC		27 /* MX50 */
 #define MXC_INT_SATA		28
 #define MXC_INT_SLIM_B		28 /* MX51 */
+#define MXC_INT_NIC		28 /* MX50 Perfmon IRQ */
 #define MXC_INT_SSI1		29
 #define MXC_INT_SSI2		30
 #define MXC_INT_UART1		31
@@ -534,6 +594,10 @@
 #define MXC_INT_SIM_IPB		67
 #define MXC_INT_SIM_DAT		68
 #define MXC_INT_IIM		69
+#define MXC_INT_ANATOP1		66 /* MX50 what's it? */
+#define MXC_INT_ANATOP2		67
+#define MXC_INT_ANATOP3		68
+#define MXC_INT_ANATOP4		69
 #define MXC_INT_ATA		70
 #define MXC_INT_CCM1		71
 #define MXC_INT_CCM2		72
@@ -559,23 +623,46 @@
 #define MXC_INT_CTI1_TG2	89
 #define MXC_INT_SJC		90
 #define MXC_INT_SPDIF_MX51		91
+#define MXC_INT_DCP_CHAN1_3	91 /* MX50 */
 #define MXC_INT_TVE		92
+#define MXC_INT_DCP_CHAN0	92 /* MX50 */
 #define MXC_INT_FIRI		93
+#define MXC_INT_DCP_CHAN0_3_SEC	93 /* MX50 */
 #define MXC_INT_PWM2		94
 #define MXC_INT_SLIM_EXP		95
 #define MXC_INT_SSI3		96
 #define MXC_INT_EMI_BOOT		97
+#define MXC_INT_RNGB_BLOCK	97 /* MX50 */
 #define MXC_INT_CTI1_TG3	98
 #define MXC_INT_SMC_RX			99
 #define MXC_INT_VPU_IDLE	100
+#define MXC_INT_RAWNAND_BCH	100 /* MX50 */
 #define MXC_INT_EMI_NFC	101
 #define MXC_INT_GPU_IDLE	102
+#define MXC_INT_RAWNAND_GPMI	102 /* MX50 */
 #define MXC_INT_GPIO5_LOW	103
 #define MXC_INT_GPIO5_HIGH	104
 #define MXC_INT_GPIO6_LOW	105
 #define MXC_INT_GPIO6_HIGH	106
 #define MXC_INT_GPIO7_LOW	107
 #define MXC_INT_GPIO7_HIGH	108
+#define MXC_INT_MSHC		109 /* MX50 */
+#define MXC_INT_APBHDMA_CHAN0	110
+#define MXC_INT_APBHDMA_CHAN1	111
+#define MXC_INT_APBHDMA_CHAN2	112
+#define MXC_INT_APBHDMA_CHAN3	113
+#define MXC_INT_APBHDMA_CHAN4	114
+#define MXC_INT_APBHDMA_CHAN5	115
+#define MXC_INT_APBHDMA_CHAN6	116
+#define MXC_INT_APBHDMA_CHAN7	117
+#define MXC_INT_APBHDMA_CHAN8	118
+#define MXC_INT_APBHDMA_CHAN9	119
+#define MXC_INT_APBHDMA_CHAN10	120
+#define MXC_INT_APBHDMA_CHAN11	121
+#define MXC_INT_APBHDMA_CHAN12	122
+#define MXC_INT_APBHDMA_CHAN13	123
+#define MXC_INT_APBHDMA_CHAN14	124
+#define MXC_INT_APBHDMA_CHAN15	125
 
 /* gpio and gpio based interrupt handling */
 #define GPIO_DR                 0x00