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authorJianzheng Zhou <jianzheng.zhou@freescale.com>2013-03-11 17:41:26 +0800
committerJianzheng Zhou <jianzheng.zhou@freescale.com>2013-03-12 10:09:06 +0800
commit66f1af42536b070268bf75cf7eceaa92150dbd20 (patch)
tree1fedcdaa0b1ce804698279368f5223f409e59092 /arch/arm/plat-mxc/include/mach/mx6.h
parent9dcb1b869fd2405efb4556a09ba512886442353e (diff)
ENGR00169384 imx6q: uart: config and enble uart5
Config clock,irq,mux pad,data entry, etc to setup uart5. Signed-off-by: Jianzheng Zhou <jianzheng.zhou@freescale.com> (cherry picked from commit 8c06604f1845028790e5da4474e4907b5f4b7504)
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx6.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx6.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h
index bb22de06a45a..ba38b8a4181e 100644
--- a/arch/arm/plat-mxc/include/mach/mx6.h
+++ b/arch/arm/plat-mxc/include/mach/mx6.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -283,6 +283,8 @@
#define MX6Q_UART2_BASE_ADDR UART2_BASE_ADDR
#define MX6Q_UART3_BASE_ADDR UART3_BASE_ADDR
#define MX6Q_UART4_BASE_ADDR UART4_BASE_ADDR
+#define MX6Q_UART5_BASE_ADDR UART5_BASE_ADDR
+
#define MX6Q_FEC_BASE_ADDR ENET_BASE_ADDR
#define MX6DL_FEC_BASE_ADDR ENET_BASE_ADDR
#define MX6Q_MIPI_DSI_BASE_ADDR MIPI_DSI_BASE_ADDR
@@ -486,6 +488,7 @@
#define MX6Q_INT_UART2 MXC_INT_UART2_ANDED
#define MX6Q_INT_UART3 MXC_INT_UART3_ANDED
#define MX6Q_INT_UART4 MXC_INT_UART4_ANDED
+#define MX6Q_INT_UART5 MXC_INT_UART5_ANDED
#define MX6SL_INT_UART1 MXC_INT_UART1_ANDED
#define MX6SL_INT_UART2 MXC_INT_UART2_ANDED
#define MX6SL_INT_UART3 MXC_INT_UART3_ANDED