diff options
author | Rob Herring <r.herring@freescale.com> | 2010-07-07 17:51:47 -0500 |
---|---|---|
committer | Richard Zhao <richard.zhao@freescale.com> | 2010-07-09 13:17:59 +0800 |
commit | eb8615f2539ab82c65dc871ee599ef4ab35112e9 (patch) | |
tree | 3ca84ebcf6f57e963b37ee128b3ab165d9662a5e /arch/arm/plat-mxc/include/mach | |
parent | 4f016161684b68e1437b5dd93abbde8eb92687dc (diff) |
ENGR00124849-3 mx5: add mx50 support
Add support for i.MX50 and arm2 board with lpddr/mddr.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Rob Herring <r.herring@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/arc_otg.h | 7 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/common.h | 1 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/memory.h | 4 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx5x.h | 58 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc.h | 15 |
5 files changed, 82 insertions, 3 deletions
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h index 1b2511079560..2a58492ccc70 100644 --- a/arch/arm/plat-mxc/include/mach/arc_otg.h +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -147,6 +147,7 @@ #define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ #define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ #define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ /* * register bits @@ -245,6 +246,7 @@ #define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ #define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ #define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ #define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */ #define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ #define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ @@ -329,6 +331,7 @@ #define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ #define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ #define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ /* USB_PHY_CTRL_FUNC2*/ #define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 #define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 @@ -355,6 +358,8 @@ #define ULPIVW_WDATA_SHIFT 0 #define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ - +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); #endif diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 742fb43592b7..990c3a00567c 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -34,6 +34,7 @@ extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mxc_init_devices(void); diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 3861342d1be0..ff05850287af 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -32,6 +32,10 @@ #define PHYS_OFFSET UL(0x90000000) #endif +#ifdef CONFIG_ARCH_MX50 +#define PHYS_OFFSET UL(0x70000000) +#endif + #ifdef CONFIG_ARCH_MX53 #define PHYS_OFFSET UL(0x70000000) #endif diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h index 44a5da1f2b64..3b9728e0a356 100644 --- a/arch/arm/plat-mxc/include/mach/mx5x.h +++ b/arch/arm/plat-mxc/include/mach/mx5x.h @@ -144,6 +144,22 @@ #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) +#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) +#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) +#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) +#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000) +#define ELCDIF_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100A000) +#define EPXP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100C000) +#define DCP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100E000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) +#define QOSC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01012000) +#define PERFMON_BASE_ADDR (DEBUG_BASE_ADDR + 0x01014000) +#define SSP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01016000) +#define ANATOP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01018000) + +#define MX50_NIC_BASE_ADDR (DEBUG_BASE_ADDR + 0x08000000) + /* * SPBA global module enabled #0 */ @@ -368,7 +384,7 @@ #define AIPS2_IO_ADDRESS(x) \ (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) -#define MX53_BASE_ADDR(x) (cpu_is_mx53() ? (x) - 0x20000000 : (x)) +#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x)) #define IS_MEM_DEVICE_NONSHARED(x) 0 @@ -385,6 +401,8 @@ #define DMA_REQ_SLIM_B_TX 42 /* MX51 */ #define DMA_REQ_UART3_TX_MX51 44 #define DMA_REQ_UART3_RX_MX51 43 +#define DMA_REQ_UART3_TX_MX50 43 +#define DMA_REQ_UART3_RX_MX50 42 #define DMA_REQ_ESAI_TX 41 #define DMA_REQ_SDHC4_MX51 41 #define DMA_REQ_ESAI_RX 40 @@ -431,9 +449,13 @@ #define DMA_REQ_UART5_RX 16 #define DMA_REQ_SPDIF_TX 15 #define DMA_REQ_SPDIF_RX 14 +#define DMA_REQ_EXTREQ0_MX50 14 +#define DMA_REQ_EXTREQ1_MX50 15 /* UART2 is shared w/FIRI on MX53 */ #define DMA_REQ_FIRI_TX 13 #define DMA_REQ_FIRI_RX 12 +#define DMA_REQ_UART2_TX_MX50 13 +#define DMA_REQ_UART2_RX_MX50 12 #define DMA_REQ_SDHC4_MX53 11 #define DMA_REQ_HS_I2C_RX 11 /* MX51 */ @@ -450,7 +472,9 @@ #define DMA_REQ_SLIM_B 5 /* MX51 */ #define DMA_REQ_ATA_TX_END 4 #define DMA_REQ_ATA_TX 3 +#define DMA_REQ_UART4_TX_MX50 3 #define DMA_REQ_ATA_RX 2 +#define DMA_REQ_UART4_RX_MX50 2 #define DMA_REQ_GPC 1 #define DMA_REQ_VPU 0 @@ -478,16 +502,21 @@ #define MXC_INT_USB_H3 17 #define MXC_INT_USB_OTG 18 #define MXC_INT_SAHARA_H0 19 +#define MXC_INT_DATABAHN 19 /* MX50 */ #define MXC_INT_SAHARA_H1 20 +#define MXC_INT_ELCDIF 20 /* MX50 */ #define MXC_INT_SCC_SMN 21 +#define MXC_INT_EPXP 21 /* MX50 */ #define MXC_INT_SCC_STZ 22 #define MXC_INT_SCC_SCM 23 #define MXC_INT_SRTC_NTZ 24 #define MXC_INT_SRTC_TZ 25 #define MXC_INT_RTIC 26 #define MXC_INT_CSU 27 +#define MXC_INT_EPDC 27 /* MX50 */ #define MXC_INT_SATA 28 #define MXC_INT_SLIM_B 28 /* MX51 */ +#define MXC_INT_NIC 28 /* MX50 Perfmon IRQ */ #define MXC_INT_SSI1 29 #define MXC_INT_SSI2 30 #define MXC_INT_UART1 31 @@ -531,6 +560,10 @@ #define MXC_INT_SIM_IPB 67 #define MXC_INT_SIM_DAT 68 #define MXC_INT_IIM 69 +#define MXC_INT_ANATOP1 66 /* MX50 what's it? */ +#define MXC_INT_ANATOP2 67 +#define MXC_INT_ANATOP3 68 +#define MXC_INT_ANATOP4 69 #define MXC_INT_ATA 70 #define MXC_INT_CCM1 71 #define MXC_INT_CCM2 72 @@ -556,23 +589,46 @@ #define MXC_INT_CTI1_TG2 89 #define MXC_INT_SJC 90 #define MXC_INT_SPDIF_MX51 91 +#define MXC_INT_DCP_CHAN1_3 91 /* MX50 */ #define MXC_INT_TVE 92 +#define MXC_INT_DCP_CHAN0 92 /* MX50 */ #define MXC_INT_FIRI 93 +#define MXC_INT_DCP_CHAN0_3_SEC 93 /* MX50 */ #define MXC_INT_PWM2 94 #define MXC_INT_SLIM_EXP 95 #define MXC_INT_SSI3 96 #define MXC_INT_EMI_BOOT 97 +#define MXC_INT_RNGB_BLOCK 97 /* MX50 */ #define MXC_INT_CTI1_TG3 98 #define MXC_INT_SMC_RX 99 #define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RAWNAND_BCH 100 /* MX50 */ #define MXC_INT_EMI_NFC 101 #define MXC_INT_GPU_IDLE 102 +#define MXC_INT_RAWNAND_GPMI 102 /* MX50 */ #define MXC_INT_GPIO5_LOW 103 #define MXC_INT_GPIO5_HIGH 104 #define MXC_INT_GPIO6_LOW 105 #define MXC_INT_GPIO6_HIGH 106 #define MXC_INT_GPIO7_LOW 107 #define MXC_INT_GPIO7_HIGH 108 +#define MXC_INT_MSHC 109 /* MX50 */ +#define MXC_INT_APBHDMA_CHAN0 110 +#define MXC_INT_APBHDMA_CHAN1 111 +#define MXC_INT_APBHDMA_CHAN2 112 +#define MXC_INT_APBHDMA_CHAN3 113 +#define MXC_INT_APBHDMA_CHAN4 114 +#define MXC_INT_APBHDMA_CHAN5 115 +#define MXC_INT_APBHDMA_CHAN6 116 +#define MXC_INT_APBHDMA_CHAN7 117 +#define MXC_INT_APBHDMA_CHAN8 118 +#define MXC_INT_APBHDMA_CHAN9 119 +#define MXC_INT_APBHDMA_CHAN10 120 +#define MXC_INT_APBHDMA_CHAN11 121 +#define MXC_INT_APBHDMA_CHAN12 122 +#define MXC_INT_APBHDMA_CHAN13 123 +#define MXC_INT_APBHDMA_CHAN14 124 +#define MXC_INT_APBHDMA_CHAN15 125 /* gpio and gpio based interrupt handling */ #define GPIO_DR 0x00 diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 91a64839c5a1..c2262f55b619 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -34,6 +34,7 @@ #define MXC_CPU_MX37 37 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 +#define MXC_CPU_MX50 50 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -147,6 +148,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx53() (0) #endif +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + #define cpu_is_mx32() (0) /* @@ -655,7 +668,7 @@ void gpio_deactivate_esai_ports(void); #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) #endif -#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53()) +#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) |