diff options
| author | Jason Jin <Jason.jin@freescale.com> | 2012-12-11 18:25:40 +0800 |
|---|---|---|
| committer | Ed Nash <enash@enash-desktop.(none)> | 2012-12-12 14:46:33 -0500 |
| commit | da9fd56e1e47c7773c8dfc4db445e3d1852d5aa5 (patch) | |
| tree | 5079c248709c082f5847f7388565dbefb1b2c627 /arch/arm/plat-mxc/include | |
| parent | a64b342273229257877df4b89879cd207289675b (diff) | |
Vybrid CAAM driver
From Singh Pradip-B09147. Integrate by Jason Jin
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include')
| -rwxr-xr-x | arch/arm/plat-mxc/include/mach/devices-common.h | 17 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mvf.h | 16 |
2 files changed, 28 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 3cdcceaea09f..0e2a2a1d13e9 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -681,3 +681,20 @@ struct imx_rngb_data { struct platform_device *__init imx_add_rngb( const struct imx_rngb_data *data); + +struct mvf_caam_jr_data { + resource_size_t offset_jr; + resource_size_t irq_jr; +}; + +struct mvf_caam_data { + resource_size_t iobase_caam; /* entirety of CAAM register map */ + resource_size_t iobase_caam_sm; /* base of secure memory */ + resource_size_t iobase_snvs; /* base of SNVS */ + resource_size_t irq_sec_vio; /* SNVS security violation */ + resource_size_t irq_snvs; /* SNVS consolidated (incl. RTC) */ + struct mvf_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */ +}; + +struct platform_device *__init mvf_add_caam( + const struct mvf_caam_data *data); diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 6512c4e2bac6..838eef400e95 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -176,6 +176,11 @@ #define MVF_SRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006E000) #define MVF_CMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006F000) +#define MVF_CAAM_SECMEM_BASE_ADDR \ + (MVF_AIPS0_BASE_ADDR + 0x0007C000) +#define MVF_CAAM_SECMEM_END_ADDR \ + (MVF_AIPS0_BASE_ADDR + 0x0007FFFF) + #define L2_BASE_ADDR MVF_L2C_BASE_ADDR #define MVF_USBC0_CTRL_BASE_ADDR 0x40034800 @@ -563,15 +568,16 @@ #define MVF_INT_ESAI_BIFIFO 120 #define MVF_INT_SPDIF 121 #define MVF_INT_ASRC 122 -#define MVF_INT_CMU 123 +#define MVF_INT_CMU 123 #define MVF_INT_WKPU0 124 #define MVF_INT_WKPU1 125 -#define MVF_INT_CCM 126 +#define MVF_INT_CCM 126 -#define MVF_INT_SRC 128 -#define MVF_INT_PDB 129 -#define MVF_INT_EWM 130 +#define MVF_INT_SRC 128 +#define MVF_INT_PDB 129 +#define MVF_INT_EWM 130 #define MVF_INT_SNVS 132 +#define MVF_INT_SNVS_SEC 133 #define MVF_INT_CAAM 134 |