diff options
| author | Mahesh Mahadevan <r9aadq@freescale.com> | 2011-10-26 16:52:48 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-01-09 21:02:59 +0800 |
| commit | 00cf4137e070a62f4cce4a714448dd127b903364 (patch) | |
| tree | b1aaca0897f0a75232d34563e4b3903c24ed60a8 /arch/arm/plat-mxc/include | |
| parent | 6a881ff9d783e68bd2233d35cdfa8ba8d99002a9 (diff) | |
ENGR00160874 Enable SSI audio support on the MX6
The MX6 Sabre-lite board uses the SGTL codec through
SSI to play audio. Add support for SSI audio on the MX6
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx6.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 284c529f56c4..d4e100df78a9 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -138,9 +138,9 @@ #define MX6Q_ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) /* slot 6 */ #define UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) /* slot 8 */ #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) /* slot 9 */ -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */ -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */ -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */ +#define MX6Q_SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */ +#define MX6Q_SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */ +#define MX6Q_SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */ #define MX6Q_ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) /* slot 13 */ #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) /* slot 15 */ #define MX6Q_VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) /* slot 33, @@ -324,9 +324,9 @@ #define MX6Q_INT_USB_OTG 75 #define MX6Q_INT_USB_PHY0 76 #define MX6Q_INT_USB_PHY1 77 -#define MXC_INT_SSI1 78 -#define MXC_INT_SSI2 79 -#define MXC_INT_SSI3 80 +#define MX6Q_INT_SSI1 78 +#define MX6Q_INT_SSI2 79 +#define MX6Q_INT_SSI3 80 #define MXC_INT_ANATOP_TEMPSNSR 81 #define MX6Q_INT_ASRC 82 #define MXC_INT_ESAI 83 |