ENGR00181390-1: qspi: Add platform support for Quad SPI driver

Add platform support for Quad SPI driver.

Signed-off-by: Alison Wang <b18965@freescale.com>
               Xiaochun Li <b41219@freescale.com>

2 files changed, 146 insertions, 0 deletions

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
index ea661abc0126..309a8ca8e621 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
@@ -310,4 +310,77 @@ typedef enum iomux_config {
 		IOMUX_PAD(0x0054, 0x0054, 0, 0x0000, 0, \
 				MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE)
 
+/*QSPI*/
+#define MVF600_PAD79_PTD0_QSPI0_A_SCK                           \
+	IOMUX_PAD(0x013C, 0x013c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW |	\
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD80_PTD1_QSPI0_A_CS0                           \
+	IOMUX_PAD(0x0140, 0x0140, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD81_PTD2_QSPI0_A_D3                            \
+	IOMUX_PAD(0x0144, 0x0144, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD82_PTD3_QSPI0_A_D2                            \
+	IOMUX_PAD(0x0148, 0x0148, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD83_PTD4_QSPI0_A_D1                            \
+	IOMUX_PAD(0x014C, 0x014c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD84_PTD5_QSPI0_A_D0                            \
+	IOMUX_PAD(0x0150, 0x0150, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD86_PTD7_QSPI0_B_SCK                           \
+	IOMUX_PAD(0x0158, 0x0158, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD87_PTD8_QSPI0_B_CS0                           \
+	IOMUX_PAD(0x015C, 0x015c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD88_PTD9_QSPI0_B_D3                            \
+	IOMUX_PAD(0x0160, 0x0160, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD89_PTD10_QSPI0_B_D2                           \
+	IOMUX_PAD(0x0164, 0x0164, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD90_PTD11_QSPI0_B_D1                           \
+	IOMUX_PAD(0x0168, 0x0168, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_PAD91_PTD12_QSPI0_B_D0                           \
+	IOMUX_PAD(0x016C, 0x016c, 1, 0x0000, 0, \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_150ohm | PAD_CTL_PUS_22K_UP | \
+			PAD_CTL_PKE | PAD_CTL_OBE_IBE_ENABLE)
+
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/spi-mvf.h b/arch/arm/plat-mxc/include/mach/spi-mvf.h
index 4a05f3b349af..0441a0f6fde5 100644
--- a/arch/arm/plat-mxc/include/mach/spi-mvf.h
+++ b/arch/arm/plat-mxc/include/mach/spi-mvf.h
@@ -97,4 +97,77 @@ struct spi_mvf_master {
 #define SPI_CS_ASSERT		0x02
 #define SPI_CS_DROP		0x04
 
+/* Quad SPI */
+#define INT_DLPFIE		(0x1 << 31)
+#define INT_TBFIE		(0x1 << 27)
+#define INT_TBUIE		(0x1 << 26)
+#define INT_ILLINIE		(0x1 << 23)
+#define INT_RBOIE		(0x1 << 17)
+#define INT_RBDIE               (0x1 << 16)
+#define INT_ABSEIE              (0x1 << 15)
+#define INT_ABOIE               (0x1 << 12)
+#define INT_IUEIE               (0x1 << 11)
+#define INT_IPAEIE              (0x1 << 7)
+#define INT_IPIEIE              (0x1 << 6)
+#define INT_IPGEIE              (0x1 << 4)
+#define INT_TFIE                (0x1 << 0)
+
+#define QUADSPI_MCR             0x00
+#define QUADSPI_IPCR            0x08
+#define QUADSPI_FLSHCR          0x0c
+#define QUADSPI_BUF0CR          0x10
+#define QUADSPI_BUF1CR          0x14
+#define QUADSPI_BUF2CR          0x18
+#define QUADSPI_BUF3CR          0x1c
+#define QUADSPI_BFGENCR         0x20
+#define QUADSPI_SOCCR           0x24
+#define QUADSPI_BUF0IND         0x30
+#define QUADSPI_BUF1IND         0x34
+#define QUADSPI_BUF2IND         0x38
+#define QUADSPI_SFAR            0x100
+#define QUADSPI_SMPR            0x108
+#define QUADSPI_RBSR            0x10c
+#define QUADSPI_RBCT            0x110
+#define QUADSPI_TBSR            0x150
+#define QUADSPI_TBDR            0x154
+#define QUADSPI_SR              0x15c
+#define QUADSPI_FR              0x160
+#define QUADSPI_RSER            0x164
+#define QUADSPI_SPNDST          0x168
+#define QUADSPI_SPTRCLR         0x16c
+#define QUADSPI_SFA1AD          0x180
+#define QUADSPI_SFA2AD          0x184
+#define QUADSPI_SFB1AD          0x188
+#define QUADSPI_SFB2AD          0x18c
+#define QUADSPI_RBDR            0x200
+#define QUADSPI_LUTKEY          0x300
+#define QUADSPI_LCKCR           0x304
+#define QUADSPI_LUT(x)          (0x310 + (x) * 4)
+
+#define OPRND0(x)               (((x) & 0xff) << 0)
+#define PAD0(x)                 (((x) & 0x3) << 8)
+#define INSTR0(x)               (((x) & 0x3f) << 10)
+
+#define OPRND1(x)               (((x) & 0xff) << 16)
+#define PAD1(x)                 (((x) & 0x3) << 24)
+#define INSTR1(x)               (((x) & 0x3f) << 26)
+
+#define SEQU_CMD		0x1
+#define SEQU_ADDR		0x2
+#define SEQU_DUMMY		0x3
+#define SEQU_MODE		0x4
+#define SEQU_MODE2		0x5
+#define SEQU_MODE4		0x6
+#define SEQU_READ		0x7
+#define SEQU_WRITE		0x8
+#define SEQU_JMP_ON_CS		0x9
+#define SEQU_ADDR_DDR		0xa
+#define SEQU_MODE_DDR		0xb
+#define SEQU_MODE2_DDR		0xc
+#define SEQU_MODE4_DDR		0xd
+#define SEQU_READ_DDR		0xe
+#define SEQU_WRITE_DDR		0xf
+#define SEQU_DATA_LEARN		0x10
+#define SEQU_STOP		0x0
+
 #endif /* SPI_MVF_H_ */