diff options
| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:34:25 +0800 |
|---|---|---|
| committer | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:52:45 +0800 |
| commit | a27cdd5fc08da3b28c4fe8c3397147c8ec6c7d7c (patch) | |
| tree | ddefa72db9e039f25d1f57444e00e7223991ad3e /arch/arm/plat-mxc | |
| parent | c87077009d68563e06b6a5d0d33e8702e8d346a0 (diff) | |
ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx6.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 48b04b104560..bb22de06a45a 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -302,6 +302,8 @@ #define SRC_GPR9 0x40 #define SRC_GPR10 0x44 +#define SNVS_LPGPR 0x68 + /* GPC offsets */ #define MXC_GPC_CNTR_OFFSET 0x0 |