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authorAnish Trivedi <anish@freescale.com>2010-04-07 16:52:50 -0500
committerAlejandro Gonzalez <alex.gonzalez@digi.com>2010-05-25 11:20:21 +0200
commitb2828ab9a09b4368b6cbad649934f1976246a22c (patch)
treec29e7810bdc801bb80a7a195e25d7004de58fbbb /arch/arm/plat-mxc
parentc78db387d42e7379a114c1b13c3ee0f69be0afd2 (diff)
ENGR00122290-1 MX5x Enable SCC2 and SAHARA drivers
Machine layer changes for MX51 and MX53 for SCC driver in order to pass base address for registers and ram as resources Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx5x.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 3770197b98bd..274a84666d53 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -75,11 +75,17 @@
#if defined(CONFIG_MXC_SECURITY_SCC2) \
|| defined(CONFIG_MXC_SECURITY_SCC2_MODULE)
-#define SCC_IRAM_SIZE SZ_16K
+#define SCC_RAM_SIZE SZ_16K
#else
-#define SCC_IRAM_SIZE 0
+#define SCC_RAM_SIZE 0
#endif
+/*
+ * SCC RAM BASE: last 2 partitions of IRAM on MX51, separate from IRAM on MX53
+ */
+#define MX51_SCC_RAM_BASE_ADDR MX51_IRAM_BASE_ADDR
+#define MX53_SCC_RAM_BASE_ADDR 0x07000000
+
#ifdef CONFIG_SND_MXC_SOC_IRAM
#define SND_RAM_SIZE 0x6000
#else