diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2009-09-17 13:17:40 -0500 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-02-12 17:19:18 +0100 |
| commit | 4baf62f99fd41eb82c66acc8cb016129f4f60a74 (patch) | |
| tree | d35b48e3928c9e8980a115e56a482bc59e737700 /arch/arm/plat-mxc | |
| parent | 12b0fdeb6d48101ccc707e72456a7f625596d962 (diff) | |
ENGR00116947: MX51: Fix the audio-pop/channel swapping issue in lp-apm mode.
In LPAPM mode, peripheral domain is clocked from the 24MHz clock.
There is a brief period of time when IPG clock drops close to 2.4MHz,
which violates the SSI to IPG clock ratio. And this causes incorrect data
to be clocked out of SSI.
Fix the code such that IPG clock does not go below 10MHz when
entering/exiting LPAPM mode.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc')
| -rw-r--r-- | arch/arm/plat-mxc/cpufreq.c | 1 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/dvfs_core.c | 25 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc_dvfs.h | 27 |
3 files changed, 33 insertions, 20 deletions
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index fab3986d301c..485be934c912 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -42,6 +42,7 @@ int cpu_freq_khz_max; int arm_lpm_clk; int arm_normal_clk; int cpufreq_suspended; +int cpufreq_trig_needed; static struct clk *cpu_clk; static struct regulator *gp_regulator; diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index 89b7e7adb8e2..40ce08a7ff7a 100644 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -76,22 +76,7 @@ #define MXC_DVFSCNTR_LTBRSR_OFFSET 3 #define MXC_DVFSCNTR_DVFEN 0x00000001 -#define MXC_GPCCNTR_GPCIRQ 0x00100000 -#define MXC_GPCCNTR_DVFS0CR 0x00010000 -#define MXC_GPCCNTR_ADU 0x00008000 -#define MXC_GPCCNTR_STRT 0x00004000 -#define MXC_GPCCNTR_FUPD 0x00002000 -#define MXC_GPCCNTR_HTRI_MASK 0x0000000F -#define MXC_GPCCNTR_HTRI_OFFSET 0 -#define MXC_GPCCNTR_GPCIRQM 0x00200000 - -#define MXC_GPCVCR_VINC_MASK 0x00020000 -#define MXC_GPCVCR_VINC_OFFSET 17 -#define MXC_GPCVCR_VCNTU_MASK 0x00010000 -#define MXC_GPCVCR_VCNTU_OFFSET 16 -#define MXC_GPCVCR_VCNT_MASK 0x00007FFF -#define MXC_GPCVCR_VCNT_OFFSET 0 - +extern int dvfs_core_is_active; extern void setup_pll(void); static struct mxc_dvfs_platform_data *dvfs_data; static struct device *dvfs_dev; @@ -99,8 +84,8 @@ static struct cpu_wp *cpu_wp_tbl; int dvfs_core_resume; int curr_wp; int old_wp; -int dvfs_core_is_active; -int cpufreq_trig_needed; + +extern int cpufreq_trig_needed; struct timeval core_prev_intr; void dump_dvfs_core_regs(void); @@ -352,9 +337,9 @@ static int start_dvfs(void) /* config reg GPC_CNTR */ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); - /* GPCIRQ=1, select ARM IRQ */ - reg |= MXC_GPCCNTR_GPCIRQ; reg &= ~MXC_GPCCNTR_GPCIRQM; + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ_ARM; /* ADU=1, select ARM domain */ reg |= MXC_GPCCNTR_ADU; __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h index 99ddb077d9d1..3a5fd7f3efa2 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -34,6 +34,33 @@ #include <linux/workqueue.h> #include <linux/device.h> +#define MXC_GPCCNTR_GPCIRQ2M (1 << 25) +#define MXC_GPCCNTR_GPCIRQ2 (1 << 24) +#define MXC_GPCCNTR_GPCIRQM (1 << 21) +#define MXC_GPCCNTR_GPCIRQ_ARM (1 << 20) +#define MXC_GPCCNTR_GPCIRQ_SDMA (0 << 20) +#define MXC_GPCCNTR_DVFS0CR (1 << 16) +#define MXC_GPCCNTR_ADU_MASK 0x8000 +#define MXC_GPCCNTR_ADU (1 << 15) +#define MXC_GPCCNTR_STRT (1 << 14) +#define MXC_GPCCNTR_FUPD_MASK 0x2000 +#define MXC_GPCCNTR_FUPD (1 << 13) +#define MXC_GPCCNTR_HTRI_MASK 0x0000000F +#define MXC_GPCCNTR_HTRI_OFFSET 0 + +#define MXC_GPCVCR_VINC_MASK 0x00020000 +#define MXC_GPCVCR_VINC_OFFSET 17 +#define MXC_GPCVCR_VCNTU_MASK 0x00010000 +#define MXC_GPCVCR_VCNTU_OFFSET 16 +#define MXC_GPCVCR_VCNT_MASK 0x00007FFF +#define MXC_GPCVCR_VCNT_OFFSET 0 + +/* DVFS-PER */ +#define MXC_DVFSPER_PMCR0_UDCS (1 << 27) +#define MXC_DVFSPER_PMCR0_UDCS_MASK 0x8000000 +#define MXC_DVFSPER_PMCR0_ENABLE_MASK 0x10 +#define MXC_DVFSPER_PMCR0_ENABLE (1 << 4) + /* * DVFS structure */ |