ENGR00117720-1 MX28: Add MSL codes to support MX28EVK

Add the MSL codes(New Framework) for MX28,
including clock, gpio, pinctrl, interrupt, timer, DMA, etc.

Signed-off-by: Fred Fan <r01011@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>

30 files changed, 4479 insertions, 0 deletions

diff --git a/arch/arm/plat-mxs/Kconfig b/arch/arm/plat-mxs/Kconfig
new file mode 100644
index 000000000000..304de21d41cc
--- /dev/null
+++ b/arch/arm/plat-mxs/Kconfig
@@ -0,0 +1,47 @@
+if ARCH_MXS
+
+menu "Freescale i.MXS implementations"
+
+choice
+	prompt "Select i.MXS chip family"
+
+config ARCH_MX28
+	bool "Freescale MX28"
+	select CPU_ARM926T
+	select ZONE_DMA
+	select MXS_ICOLL
+	select MXS_DMA_ENGINE
+	---help---
+	 Support Freescale MX28 chips
+
+endchoice
+
+if ARCH_MX28
+source arch/arm/mach-mx28/Kconfig
+endif
+
+config DMA_ZONE_SIZE
+	int "DMA memory zone size"
+	range 0 32
+	default 16
+	help
+	    This is the size in MB for the DMA zone. The DMA zone is used for
+	    dedicated memory for large contiguous video buffers
+endmenu
+
+config MXS_ICOLL
+	bool
+
+config MXS_EARLY_CONSOLE
+	bool "Enable console early"
+	default y
+	help
+	  Enable console early for kernel debug.
+
+config MXS_DMA_ENGINE
+	bool "Enable DMA ENGINE support"
+	default y
+	help
+	  Support DMA controller on AHB-APBH and AHB-APBX Bridge
+
+endif
diff --git a/arch/arm/plat-mxs/Makefile b/arch/arm/plat-mxs/Makefile
new file mode 100644
index 000000000000..aa7a2c5cf167
--- /dev/null
+++ b/arch/arm/plat-mxs/Makefile
@@ -0,0 +1,16 @@
+#
+# Makefile for the linux kernel.
+#
+# Object file lists.
+obj-y += core.o clock.o pinctrl.o device.o timer.o
+
+obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+
+obj-$(CONFIG_MXS_ICOLL) += icoll.o
+
+obj-$(CONFIG_MXS_DMA_ENGINE) += dmaengine.o dma-apbh.o dma-apbx.o
+
+# Power Management
+
+# charging/current limitation testing
+
diff --git a/arch/arm/plat-mxs/clock.c b/arch/arm/plat-mxs/clock.c
new file mode 100644
index 000000000000..a4bd61cb699e
--- /dev/null
+++ b/arch/arm/plat-mxs/clock.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+
+#include <mach/clock.h>
+
+static DEFINE_SPINLOCK(clockfw_lock);
+
+/*
+ *-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------
+ */
+int __clk_get(struct clk *clk)
+{
+	if (clk->ref < CLK_REF_LIMIT)
+		clk->ref += CLK_REF_UNIT;
+	return clk->ref < CLK_REF_LIMIT;
+}
+
+void __clk_put(struct clk *clk)
+{
+	if (clk->ref & CLK_REF_LIMIT)
+		clk->ref -= CLK_REF_UNIT;
+}
+
+static void default_clk_disable(struct clk *clk)
+{
+	if (clk->enable_reg)
+		__raw_writel(clk->enable_bits, clk->enable_reg + SET_REGISTER);
+}
+
+static int default_clk_enable(struct clk *clk)
+{
+	if (clk->enable_reg)
+		__raw_writel(clk->enable_bits, clk->enable_reg + CLR_REGISTER);
+	return 0;
+}
+
+static unsigned long default_get_rate(struct clk *clk)
+{
+	if (clk->parent && clk->parent->get_rate)
+		return clk->parent->get_rate(clk->parent);
+	return 0L;
+}
+
+static void __clk_disable(struct clk *clk)
+{
+	if (clk == NULL || IS_ERR(clk) || !clk->ref)
+		return;
+
+	if ((--clk->ref) & CLK_EN_MASK)
+		return;
+
+	if (clk->disable)
+		clk->disable(clk);
+	__clk_disable(clk->secondary);
+	__clk_disable(clk->parent);
+}
+
+static int __clk_enable(struct clk *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return -EINVAL;
+
+	if ((clk->ref++) & CLK_EN_MASK)
+		return 0;
+	if (clk->parent)
+		__clk_enable(clk->parent);
+	if (clk->secondary)
+		__clk_enable(clk->secondary);
+	if (clk->enable)
+		clk->enable(clk);
+	return 0;
+}
+
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+	int ret = 0;
+
+	if (clk == NULL || IS_ERR(clk))
+		return -EINVAL;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+	ret = __clk_enable(clk);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	if (clk == NULL || IS_ERR(clk))
+		return;
+	if (clk->flags & ALWAYS_ENABLED)
+		return;
+	spin_lock_irqsave(&clockfw_lock, flags);
+	__clk_disable(clk);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+int clk_get_usecount(struct clk *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return -EINVAL;
+	return clk->ref & CLK_EN_MASK;
+}
+EXPORT_SYMBOL(clk_get_usecount);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	unsigned long flags, rate;
+	if (clk == NULL || IS_ERR(clk) || clk->get_rate == NULL)
+		return 0UL;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+	rate = clk->get_rate(clk);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+	return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
+		return 0;
+
+	if (clk->flags & RATE_FIXED)
+		return 0;
+
+	if (clk->round_rate)
+		return clk->round_rate(clk, rate);
+	return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+
+	if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
+		return ret;
+
+	if (clk->flags & RATE_FIXED)
+		return ret;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+	ret = clk->set_rate(clk, rate);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+	struct clk *prev_parent;
+
+	if (clk == NULL || IS_ERR(clk) || parent == NULL ||
+	    IS_ERR(parent) || clk->set_parent == NULL ||
+	    parent->get_rate == NULL)
+		return ret;
+
+	if (clk->ref & CLK_EN_MASK)
+		clk_enable(parent);
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+	prev_parent = clk->parent;
+	ret = clk->set_parent(clk, parent);
+	if (ret) {
+		spin_unlock_irqrestore(&clockfw_lock, flags);
+		if (clk->ref & CLK_EN_MASK)
+			clk_disable(parent);
+		return ret;
+	}
+
+	clk->parent = parent;
+
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+
+	if (clk->ref & CLK_EN_MASK)
+		clk_disable(prev_parent);
+	return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	struct clk *ret = NULL;
+
+	if (clk == NULL || IS_ERR(clk))
+		return ret;
+
+	return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+int clk_register(struct clk_lookup *lookup)
+{
+	if (lookup == NULL || IS_ERR(lookup) ||
+	    lookup->clk == NULL || IS_ERR(lookup->clk))
+		return -EINVAL;
+
+	if (lookup->clk->ref & CLK_REF_LIMIT)
+		return -EEXIST;
+
+	if (!(lookup->clk->enable))
+		lookup->clk->enable = default_clk_enable;
+	if (!(lookup->clk->disable))
+		lookup->clk->disable = default_clk_disable;
+	if (!(lookup->clk->get_rate))
+		lookup->clk->get_rate = default_get_rate;
+
+	clkdev_add(lookup);
+
+	return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+void clk_unregister(struct clk_lookup *lookup)
+{
+	if (lookup == NULL || IS_ERR(lookup) ||
+	    lookup->clk == NULL || IS_ERR(lookup->clk))
+		return;
+
+	if (lookup->clk->ref & CLK_REF_LIMIT)
+		return;
+
+	clkdev_drop(lookup);
+	if (lookup->clk->enable == default_clk_enable)
+		lookup->clk->enable = NULL;
+	if (lookup->clk->disable == default_clk_disable)
+		lookup->clk->disable = NULL;
+	if (lookup->clk->get_rate == default_get_rate)
+		lookup->clk->get_rate = NULL;
+}
+EXPORT_SYMBOL(clk_unregister);
diff --git a/arch/arm/plat-mxs/core.c b/arch/arm/plat-mxs/core.c
new file mode 100644
index 000000000000..7f91808e6c66
--- /dev/null
+++ b/arch/arm/plat-mxs/core.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <asm/proc-fns.h>
+
+static void (*machine_arch_reset) (char mode, const char *cmd);
+
+void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+void arch_reset(char mode, const char *cmd)
+{
+	if (machine_arch_reset)
+		machine_arch_reset(mode, cmd);
+}
+
+static int __mxs_reset_block(void __iomem *hwreg, int just_enable)
+{
+	u32 c;
+	int timeout;
+
+	/* the process of software reset of IP block is done
+	   in several steps:
+
+	   - clear SFTRST and wait for block is enabled;
+	   - clear clock gating (CLKGATE bit);
+	   - set the SFTRST again and wait for block is in reset;
+	   - clear SFTRST and wait for reset completion.
+	 */
+	c = __raw_readl(hwreg);
+	c &= ~(1 << 31);	/* clear SFTRST */
+	__raw_writel(c, hwreg);
+	for (timeout = 1000000; timeout > 0; timeout--)
+		/* still in SFTRST state ? */
+		if ((__raw_readl(hwreg) & (1 << 31)) == 0)
+			break;
+	if (timeout <= 0) {
+		printk(KERN_ERR "%s(%p): timeout when enabling\n",
+		       __func__, hwreg);
+		return -ETIME;
+	}
+
+	c = __raw_readl(hwreg);
+	c &= ~(1 << 30);	/* clear CLKGATE */
+	__raw_writel(c, hwreg);
+
+	if (!just_enable) {
+		c = __raw_readl(hwreg);
+		c |= (1 << 31);	/* now again set SFTRST */
+		__raw_writel(c, hwreg);
+		for (timeout = 1000000; timeout > 0; timeout--)
+			/* poll until CLKGATE set */
+			if (__raw_readl(hwreg) & (1 << 30))
+				break;
+		if (timeout <= 0) {
+			printk(KERN_ERR "%s(%p): timeout when resetting\n",
+			       __func__, hwreg);
+			return -ETIME;
+		}
+
+		c = __raw_readl(hwreg);
+		c &= ~(1 << 31);	/* clear SFTRST */
+		__raw_writel(c, hwreg);
+		for (timeout = 1000000; timeout > 0; timeout--)
+			/* still in SFTRST state ? */
+			if ((__raw_readl(hwreg) & (1 << 31)) == 0)
+				break;
+		if (timeout <= 0) {
+			printk(KERN_ERR "%s(%p): timeout when enabling "
+			       "after reset\n", __func__, hwreg);
+			return -ETIME;
+		}
+
+		c = __raw_readl(hwreg);
+		c &= ~(1 << 30);	/* clear CLKGATE */
+		__raw_writel(c, hwreg);
+	}
+	for (timeout = 1000000; timeout > 0; timeout--)
+		/* still in SFTRST state ? */
+		if ((__raw_readl(hwreg) & (1 << 30)) == 0)
+			break;
+
+	if (timeout <= 0) {
+		printk(KERN_ERR "%s(%p): timeout when unclockgating\n",
+		       __func__, hwreg);
+		return -ETIME;
+	}
+
+	return 0;
+}
+
+int mxs_reset_block(void __iomem *hwreg, int just_enable)
+{
+	int try = 10;
+	int r;
+
+	while (try--) {
+		r = __mxs_reset_block(hwreg, just_enable);
+		if (!r)
+			break;
+		pr_debug("%s: try %d failed\n", __func__, 10 - try);
+	}
+	return r;
+}
diff --git a/arch/arm/plat-mxs/device.c b/arch/arm/plat-mxs/device.c
new file mode 100644
index 000000000000..9c9c6222127f
--- /dev/null
+++ b/arch/arm/plat-mxs/device.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+
+#include <mach/device.h>
+
+static int mxs_device_num;
+static int mxs_device_done;
+static DEFINE_MUTEX(device_mutex);
+static struct list_head mxs_device_level[] = {
+	LIST_HEAD_INIT(mxs_device_level[0]),
+	LIST_HEAD_INIT(mxs_device_level[1]),
+	LIST_HEAD_INIT(mxs_device_level[2]),
+	LIST_HEAD_INIT(mxs_device_level[3]),
+};
+
+void mxs_nop_release(struct device *dev)
+{
+	/* Nothing */
+}
+
+int mxs_add_devices(struct platform_device *pdev, int num, int level)
+{
+	int i, ret = -ENOMEM;
+	if (pdev == NULL || IS_ERR(pdev) || num <= 0)
+		return -EINVAL;
+
+	if (level < 0)
+		level = 0;
+	else if (level >= ARRAY_SIZE(mxs_device_level))
+		level = ARRAY_SIZE(mxs_device_level) - 1;
+
+	mutex_lock(&device_mutex);
+	if (mxs_device_done) {
+		ret = 0;
+		for (i = 0; i < num; i++)
+			ret |= platform_device_register(pdev + i);
+		goto out;
+	}
+
+	if ((mxs_device_num + num) > MXS_MAX_DEVICES)
+		goto out;
+	mxs_device_num += num;
+	for (i = 0; i < num; i++)
+		list_add_tail(&pdev[i].dev.devres_head,
+			      &mxs_device_level[level]);
+	ret = 0;
+out:
+	mutex_unlock(&device_mutex);
+	return ret;
+}
+
+int mxs_add_device(struct platform_device *pdev, int level)
+{
+	return mxs_add_devices(pdev, 1, level);
+}
+
+#if defined(CONFIG_SERIAL_MXS_DUART) || \
+	defined(CONFIG_SERIAL_MXS_DUART_MODULE)
+static struct platform_device mxs_duart = {
+	.name = "mxs-duart",
+	.id = 0,
+	.dev = {
+		.release = mxs_nop_release,
+		},
+};
+#endif
+
+#if defined(CONFIG_MXS_DMA_ENGINE)
+static struct platform_device mxs_dma[] = {
+	{
+	 .name = "mxs-dma-apbh",
+	 .id = 0,
+	 .dev = {
+		 .release = mxs_nop_release,
+		 },
+	 },
+	{
+	 .name = "mxs-dma-apbx",
+	 .id = 0,
+	 .dev = {
+		 .release = mxs_nop_release,
+		 },
+	 },
+};
+#endif
+
+static struct mxs_dev_lookup dev_lookup[] = {
+#if defined(CONFIG_SERIAL_MXS_DUART) || \
+	defined(CONFIG_SERIAL_MXS_DUART_MODULE)
+	{
+	 .name = "mxs-duart",
+	 .size = 1,
+	 .pdev = &mxs_duart,
+	 },
+#endif
+#if defined(CONFIG_MXS_DMA_ENGINE)
+	{
+	 .name = "mxs-dma",
+	 .size = ARRAY_SIZE(mxs_dma),
+	 .pdev = mxs_dma,
+	 },
+#endif
+};
+
+struct platform_device *mxs_get_device(char *name, int id)
+{
+	int i, j;
+	struct mxs_dev_lookup *lookup;
+	struct platform_device *pdev = (struct platform_device *)-ENODEV;
+	if (name == NULL || id < 0 || IS_ERR(name))
+		return (struct platform_device *)-EINVAL;
+
+	mutex_lock(&device_mutex);
+	for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) {
+		lookup = &dev_lookup[i];
+		if (!strcmp(name, lookup->name)) {
+			if (test_bit(0, &lookup->lock)) {
+				pdev = (struct platform_device *)-EBUSY;
+				break;
+			}
+
+			if (id >= lookup->size)
+				break;
+			for (j = 0; j < lookup->size; j++) {
+				if (id == (lookup->pdev[j]).id) {
+					pdev = &lookup->pdev[j];
+					break;
+				}
+			}
+			break;
+		}
+
+	}
+	mutex_unlock(&device_mutex);
+	return pdev;
+}
+
+struct mxs_dev_lookup *mxs_get_devices(char *name)
+{
+	int i;
+	struct mxs_dev_lookup *lookup;
+	if (name == NULL || IS_ERR(name))
+		return (struct mxs_dev_lookup *)-EINVAL;
+
+	mutex_lock(&device_mutex);
+	for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) {
+		lookup = &dev_lookup[i];
+		if (!strcmp(name, lookup->name)) {
+			if (test_and_set_bit(0, &lookup->lock))
+				lookup = (struct mxs_dev_lookup *)-EBUSY;
+			mutex_unlock(&device_mutex);
+			return lookup;
+		}
+
+	}
+	mutex_unlock(&device_mutex);
+	return (struct mxs_dev_lookup *)-ENODEV;
+}
+
+int mxs_device_init(void)
+{
+	int i, ret = 0;
+	struct list_head *p, *n;
+	struct device *dev;
+	struct platform_device *pdev;
+	mutex_lock(&device_mutex);
+	mxs_device_done = 1;
+	mutex_unlock(&device_mutex);
+
+	for (i = 0; i < ARRAY_SIZE(mxs_device_level); i++) {
+		list_for_each_safe(p, n, mxs_device_level + i) {
+			dev = list_entry(p, struct device, devres_head);
+			list_del(p);
+			pdev = container_of(dev, struct platform_device, dev);
+			ret |= platform_device_register(pdev);
+		}
+	}
+
+	return ret;
+}
+
+device_initcall(mxs_device_init);
diff --git a/arch/arm/plat-mxs/dma-apbh.c b/arch/arm/plat-mxs/dma-apbh.c
new file mode 100644
index 000000000000..221ff491cbea
--- /dev/null
+++ b/arch/arm/plat-mxs/dma-apbh.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/dmapool.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/device.h>
+#include <mach/dmaengine.h>
+
+#include "regs-apbh.h"
+
+static int mxs_dma_apbh_enable(struct mxs_dma_chan *pchan, unsigned int chan)
+{
+	unsigned int sem;
+	struct mxs_dma_device *pdev = pchan->dma;
+	struct mxs_dma_desc *pdesc;
+
+	pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
+	if (pdesc == NULL)
+		return -EFAULT;
+
+	sem = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan));
+	sem = (sem & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE;
+	if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
+		if (pdesc->cmd.cmd.bits.chain == 0)
+			return 0;
+		if (sem < 2) {
+			if (!sem)
+				return 0;
+			pdesc = list_entry(pdesc->node.next,
+					   struct mxs_dma_desc, node);
+			__raw_writel(mxs_dma_cmd_address(pdesc),
+				     pdev->base + HW_APBH_CHn_NXTCMDAR(chan));
+		}
+		sem = pchan->pending_num;
+		pchan->pending_num = 0;
+		__raw_writel(BF_APBH_CHn_SEMA_INCREMENT_SEMA(sem),
+			     pdev->base + HW_APBH_CHn_SEMA(chan));
+		pchan->active_num += sem;
+		return 0;
+	}
+	pchan->active_num += pchan->pending_num;
+	pchan->pending_num = 0;
+	__raw_writel(mxs_dma_cmd_address(pdesc),
+		     pdev->base + HW_APBH_CHn_NXTCMDAR(chan));
+	__raw_writel(pchan->active_num, pdev->base + HW_APBH_CHn_SEMA(chan));
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_CLR);
+	return 0;
+}
+
+static void mxs_dma_apbh_disable(struct mxs_dma_chan *pchan, unsigned int chan)
+{
+	struct mxs_dma_device *pdev = pchan->dma;
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_SET);
+}
+
+static void mxs_dma_apbh_reset(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << (chan + BP_APBH_CHANNEL_CTRL_RESET_CHANNEL),
+		     pdev->base + HW_APBH_CHANNEL_CTRL_SET);
+}
+
+static void mxs_dma_apbh_freeze(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_SET);
+}
+
+static void
+mxs_dma_apbh_unfreeze(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_CLR);
+}
+
+static int
+mxs_dma_apbh_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	unsigned int reg;
+	reg = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan));
+	return (reg & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE;
+}
+
+static void
+mxs_dma_apbh_enable_irq(struct mxs_dma_device *pdev,
+			unsigned int chan, int enable)
+{
+	if (enable) {
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_SET);
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL2_SET);
+	} else {
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_CLR);
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL2_CLR);
+	}
+}
+
+static int
+mxs_dma_apbh_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	unsigned int reg;
+	reg = __raw_readl(pdev->base + HW_APBH_CTRL1);
+	reg |= __raw_readl(pdev->base + HW_APBH_CTRL2);
+	return reg & (1 << chan);
+}
+
+static void mxs_dma_apbh_ack_irq(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CTRL1_CLR);
+	__raw_writel(1 << chan, pdev->base + HW_APBH_CTRL2_CLR);
+}
+
+static struct mxs_dma_device mxs_dma_apbh = {
+	.name = "mxs-dma-apbh",
+	.enable = mxs_dma_apbh_enable,
+	.disable = mxs_dma_apbh_disable,
+	.reset = mxs_dma_apbh_reset,
+	.freeze = mxs_dma_apbh_freeze,
+	.unfreeze = mxs_dma_apbh_unfreeze,
+	.read_semaphore = mxs_dma_apbh_read_semaphore,
+	.enable_irq = mxs_dma_apbh_enable_irq,
+	.irq_is_pending = mxs_dma_apbh_irq_is_pending,
+	.ack_irq = mxs_dma_apbh_ack_irq,
+};
+
+static int __devinit dma_apbh_probe(struct platform_device *pdev)
+{
+	int i;
+	struct resource *res;
+	struct mxs_dma_plat_data *plat;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOMEM;
+	mxs_dma_apbh.base = IO_ADDRESS(res->start);
+	__raw_writel(BM_APBH_CTRL0_SFTRST,
+		     mxs_dma_apbh.base + HW_APBH_CTRL0_CLR);
+	for (i = 0; i < 10000; i++) {
+		if (!(__raw_readl(mxs_dma_apbh.base + HW_APBH_CTRL0_CLR) &
+		      BM_APBH_CTRL0_SFTRST))
+			break;
+		udelay(2);
+	}
+	if (i >= 10000)
+		return -ETIME;
+	__raw_writel(BM_APBH_CTRL0_CLKGATE,
+		     mxs_dma_apbh.base + HW_APBH_CTRL0_CLR);
+
+	plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data;
+	if (!plat)
+		return -ENODEV;
+	if (plat->burst8)
+		__raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN,
+			     mxs_dma_apbh.base + HW_APBH_CTRL0_SET);
+	else
+		__raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN,
+			     mxs_dma_apbh.base + HW_APBH_CTRL0_CLR);
+
+	if (plat->burst)
+		__raw_writel(BM_APBH_CTRL0_APB_BURST_EN,
+			     mxs_dma_apbh.base + HW_APBH_CTRL0_SET);
+	else
+		__raw_writel(BM_APBH_CTRL0_APB_BURST_EN,
+			     mxs_dma_apbh.base + HW_APBH_CTRL0_CLR);
+
+	mxs_dma_apbh.pdev = pdev;
+	mxs_dma_apbh.chan_base = plat->chan_base;
+	mxs_dma_apbh.chan_num = plat->chan_num;
+	platform_set_drvdata(pdev, &mxs_dma_apbh);
+	return mxs_dma_device_register(&mxs_dma_apbh);
+}
+
+static int __devexit dma_apbh_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver dma_apbh_driver = {
+	.probe = dma_apbh_probe,
+	.remove = __devexit_p(dma_apbh_remove),
+	.driver = {
+		   .name = "mxs-dma-apbh"},
+};
+
+static int __init mxs_dma_apbh_init(void)
+{
+	return platform_driver_register(&dma_apbh_driver);
+}
+
+fs_initcall(mxs_dma_apbh_init);
diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c
new file mode 100644
index 000000000000..40d299e9e812
--- /dev/null
+++ b/arch/arm/plat-mxs/dma-apbx.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/dmapool.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/device.h>
+#include <mach/dmaengine.h>
+
+#include "regs-apbx.h"
+
+static int mxs_dma_apbx_enable(struct mxs_dma_chan *pchan, unsigned int chan)
+{
+	unsigned int sem;
+	struct mxs_dma_device *pdev = pchan->dma;
+	struct mxs_dma_desc *pdesc;
+
+	pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
+	if (pdesc == NULL)
+		return -EFAULT;
+	sem = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan));
+	sem = (sem & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE;
+	if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
+		if (pdesc->cmd.cmd.bits.chain == 0)
+			return 0;
+		if (sem < 2) {
+			if (!sem)
+				return 0;
+			pdesc = list_entry(pdesc->node.next,
+					   struct mxs_dma_desc, node);
+			__raw_writel(mxs_dma_cmd_address(pdesc),
+				     pdev->base + HW_APBX_CHn_NXTCMDAR(chan));
+		}
+		sem = pchan->pending_num;
+		pchan->pending_num = 0;
+		__raw_writel(BF_APBX_CHn_SEMA_INCREMENT_SEMA(sem),
+			     pdev->base + HW_APBX_CHn_SEMA(chan));
+		pchan->active_num += sem;
+		return 0;
+	}
+	pchan->active_num += pchan->pending_num;
+	pchan->pending_num = 0;
+	__raw_writel(mxs_dma_cmd_address(pdesc),
+		     pdev->base + HW_APBX_CHn_NXTCMDAR(chan));
+	__raw_writel(pchan->active_num, pdev->base + HW_APBX_CHn_SEMA(chan));
+	return 0;
+}
+
+static void mxs_dma_apbx_disable(struct mxs_dma_chan *pchan, unsigned int chan)
+{
+	struct mxs_dma_device *pdev = pchan->dma;
+	__raw_writel(0, pdev->base + HW_APBX_CHn_SEMA(chan));
+}
+
+static void mxs_dma_apbx_reset(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << (chan + BP_APBX_CHANNEL_CTRL_RESET_CHANNEL),
+		     pdev->base + HW_APBX_CHANNEL_CTRL_SET);
+}
+
+static void mxs_dma_apbx_freeze(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_SET);
+}
+
+static void
+mxs_dma_apbx_unfreeze(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_CLR);
+}
+
+static int
+mxs_dma_apbx_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	unsigned int reg;
+	reg = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan));
+	return (reg & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE;
+}
+
+static void
+mxs_dma_apbx_enable_irq(struct mxs_dma_device *pdev,
+			unsigned int chan, int enable)
+{
+	if (enable) {
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_SET);
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL2_SET);
+	} else {
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_CLR);
+		__raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL2_CLR);
+	}
+}
+
+static int
+mxs_dma_apbx_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	unsigned int reg;
+	reg = __raw_readl(pdev->base + HW_APBX_CTRL1);
+	reg |= __raw_readl(pdev->base + HW_APBX_CTRL2);
+	return reg & (1 << chan);
+}
+
+static void mxs_dma_apbx_ack_irq(struct mxs_dma_device *pdev, unsigned int chan)
+{
+	__raw_writel(1 << chan, pdev->base + HW_APBX_CTRL1_CLR);
+	__raw_writel(1 << chan, pdev->base + HW_APBX_CTRL2_CLR);
+}
+
+static struct mxs_dma_device mxs_dma_apbx = {
+	.name = "mxs-dma-apbx",
+	.enable = mxs_dma_apbx_enable,
+	.disable = mxs_dma_apbx_disable,
+	.reset = mxs_dma_apbx_reset,
+	.freeze = mxs_dma_apbx_freeze,
+	.unfreeze = mxs_dma_apbx_unfreeze,
+	.read_semaphore = mxs_dma_apbx_read_semaphore,
+	.enable_irq = mxs_dma_apbx_enable_irq,
+	.irq_is_pending = mxs_dma_apbx_irq_is_pending,
+	.ack_irq = mxs_dma_apbx_ack_irq,
+};
+
+static int __devinit dma_apbx_probe(struct platform_device *pdev)
+{
+	int i;
+	struct resource *res;
+	struct mxs_dma_plat_data *plat;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENOMEM;
+	mxs_dma_apbx.base = IO_ADDRESS(res->start);
+	__raw_writel(BM_APBX_CTRL0_SFTRST,
+		     mxs_dma_apbx.base + HW_APBX_CTRL0_CLR);
+	for (i = 0; i < 10000; i++) {
+		if (!(__raw_readl(mxs_dma_apbx.base + HW_APBX_CTRL0_CLR) &
+		      BM_APBX_CTRL0_SFTRST))
+			break;
+		udelay(2);
+	}
+	if (i >= 10000)
+		return -ETIME;
+	__raw_writel(BM_APBX_CTRL0_CLKGATE,
+		     mxs_dma_apbx.base + HW_APBX_CTRL0_CLR);
+
+	plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data;
+	if (!plat)
+		return -ENODEV;
+
+	mxs_dma_apbx.pdev = pdev;
+	mxs_dma_apbx.chan_base = plat->chan_base;
+	mxs_dma_apbx.chan_num = plat->chan_num;
+	platform_set_drvdata(pdev, &mxs_dma_apbx);
+	return mxs_dma_device_register(&mxs_dma_apbx);
+}
+
+static int __devexit dma_apbx_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver dma_apbx_driver = {
+	.probe = dma_apbx_probe,
+	.remove = __devexit_p(dma_apbx_remove),
+	.driver = {
+		   .name = "mxs-dma-apbx"},
+};
+
+static int __init mxs_dma_apbx_init(void)
+{
+	return platform_driver_register(&dma_apbx_driver);
+}
+
+fs_initcall(mxs_dma_apbx_init);
diff --git a/arch/arm/plat-mxs/dmaengine.c b/arch/arm/plat-mxs/dmaengine.c
new file mode 100644
index 000000000000..c3e592c1bdff
--- /dev/null
+++ b/arch/arm/plat-mxs/dmaengine.c
@@ -0,0 +1,579 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/dmapool.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <mach/dma.h>
+#include <mach/dmaengine.h>
+
+static void *mxs_dma_pool;
+static int mxs_dma_alignment = MXS_DMA_ALIGNMENT;
+static DEFINE_MUTEX(mxs_dma_mutex);
+static LIST_HEAD(mxs_dma_devices);
+static struct mxs_dma_chan mxs_dma_channels[MAX_DMA_CHANNELS];
+
+int mxs_dma_request(int channel, struct device *dev, const char *name)
+{
+	int ret = 0;
+	struct mxs_dma_chan *pchan;
+
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+
+	if (!dev || !name)
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	mutex_lock(&mxs_dma_mutex);
+	if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) {
+		ret = -ENODEV;
+		goto out;
+	}
+	if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) {
+		ret = -EBUSY;
+		goto out;
+	}
+	pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
+	pchan->name = name;
+	pchan->dev = (unsigned long)dev;
+	pchan->active_num = 0;
+	pchan->pending_num = 0;
+	spin_lock_init(&pchan->lock);
+	INIT_LIST_HEAD(&pchan->active);
+	INIT_LIST_HEAD(&pchan->done);
+out:
+	mutex_unlock(&mxs_dma_mutex);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_request);
+
+void mxs_dma_release(int channel, struct device *dev)
+{
+	struct mxs_dma_chan *pchan;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+
+	if (pchan->flags & MXS_DMA_FLAGS_BUSY)
+		return;
+
+	if (pchan->dev != (unsigned long)dev)
+		return;
+
+	mutex_lock(&mxs_dma_mutex);
+	pchan->dev = 0;
+	pchan->active_num = 0;
+	pchan->pending_num = 0;
+	pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
+	mutex_unlock(&mxs_dma_mutex);
+}
+EXPORT_SYMBOL(mxs_dma_release);
+
+int mxs_dma_enable(int channel)
+{
+	int ret = 0;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return -EINVAL;
+
+	pdma = pchan->dma;
+	mutex_lock(&mxs_dma_mutex);
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pchan->pending_num && pdma->enable)
+		ret = pdma->enable(pchan, channel - pdma->chan_base);
+	pchan->flags |= MXS_DMA_FLAGS_BUSY;
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	mutex_unlock(&mxs_dma_mutex);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_enable);
+
+void mxs_dma_disable(int channel)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
+		return;
+	pdma = pchan->dma;
+	mutex_lock(&mxs_dma_mutex);
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->disable)
+		pdma->disable(pchan, channel - pdma->chan_base);
+	pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+	pchan->active_num = 0;
+	pchan->pending_num = 0;
+	list_splice(&pchan->active, &pchan->done);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	mutex_unlock(&mxs_dma_mutex);
+}
+EXPORT_SYMBOL(mxs_dma_disable);
+
+int mxs_dma_cooked(int channel, struct list_head *head)
+{
+	int sem;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct list_head *p, *q;
+	struct mxs_dma_desc *pdesc;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return -EINVAL;
+
+	sem = mxs_dma_read_semaphore(channel);
+	if (sem < 0)
+		return sem;
+	spin_lock_irqsave(&pchan->lock, flags);
+	list_for_each_safe(p, q, &pchan->active) {
+		if ((pchan->active_num) <= sem)
+			break;
+		pdesc = list_entry(p, struct mxs_dma_desc, node);
+		pdesc->flags &= ~MXS_DMA_DESC_READY;
+		if (head)
+			list_move_tail(p, head);
+		else
+			list_move_tail(p, &pchan->done);
+		pchan->active_num--;
+	}
+	if (sem == 0)
+		pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+	spin_unlock_irqrestore(&pchan->lock, flags);
+
+	BUG_ON(sem != pchan->active_num);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_dma_cooked);
+
+void mxs_dma_reset(int channel)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->reset)
+		pdma->reset(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_reset);
+
+void mxs_dma_freeze(int channel)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->freeze)
+		pdma->freeze(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_freeze);
+
+void mxs_dma_unfreeze(int channel)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->unfreeze)
+		pdma->unfreeze(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_unfreeze);
+
+int mxs_dma_read_semaphore(int channel)
+{
+	int ret = -EINVAL;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return ret;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return ret;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->read_semaphore)
+		ret = pdma->read_semaphore(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_read_semaphore);
+
+void mxs_dma_enable_irq(int channel, int en)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->enable_irq)
+		pdma->enable_irq(pdma, channel - pdma->chan_base, en);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_enable_irq);
+
+int mxs_dma_irq_is_pending(int channel)
+{
+	int ret = 0;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return ret;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return ret;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->irq_is_pending)
+		ret = pdma->irq_is_pending(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_irq_is_pending);
+
+void mxs_dma_ack_irq(int channel)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->ack_irq)
+		pdma->ack_irq(pdma, channel - pdma->chan_base);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_ack_irq);
+
+void mxs_dma_set_target(int channel, int target)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return;
+	if (pchan->flags & MXS_DMA_FLAGS_BUSY)
+		return;
+	pdma = pchan->dma;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (pdma->set_target)
+		pdma->set_target(pdma, channel - pdma->chan_base, target);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+}
+EXPORT_SYMBOL(mxs_dma_set_target);
+
+/* mxs dma utility function */
+struct mxs_dma_desc *mxs_dma_alloc_desc(void)
+{
+	struct mxs_dma_desc *pdesc;
+	unsigned int address;
+	if (mxs_dma_pool == NULL)
+		return NULL;
+
+	pdesc = dma_pool_alloc(mxs_dma_pool, GFP_KERNEL, &address);
+	if (pdesc == NULL)
+		return NULL;
+	memset(pdesc, 0, sizeof(*pdesc));
+	pdesc->address = address;
+	return pdesc;
+};
+EXPORT_SYMBOL(mxs_dma_alloc_desc);
+
+void mxs_dma_free_desc(struct mxs_dma_desc *pdesc)
+{
+	if (pdesc == NULL)
+		return;
+
+	if (mxs_dma_pool == NULL)
+		return;
+
+	dma_pool_free(mxs_dma_pool, pdesc, pdesc->address);
+}
+EXPORT_SYMBOL(mxs_dma_free_desc);
+
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
+{
+	int ret = 0;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_desc *last;
+	struct mxs_dma_device *pdma;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return -EINVAL;
+	pdma = pchan->dma;
+	pdesc->cmd.next = 0;
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (!list_empty(&pchan->active)) {
+		last = list_entry(pchan->active.prev,
+				  struct mxs_dma_desc, node);
+		pdesc->cmd.next = last->cmd.next;
+		last->cmd.next = mxs_dma_cmd_address(pdesc);
+		if (pdesc->cmd.cmd.bits.chain) {
+			last->cmd.cmd.bits.chain = 1;
+			pdesc->cmd.cmd.bits.chain = 0;
+		}
+	}
+	pdesc->flags |= MXS_DMA_DESC_READY;
+	pchan->pending_num++;
+	list_add_tail(&pdesc->node, &pchan->active);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_desc_append);
+
+int mxs_dma_desc_add_list(int channel, struct list_head *head)
+{
+	int ret = 0, size = 0;
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	struct mxs_dma_device *pdma;
+	struct list_head *p;
+	struct mxs_dma_desc *prev = NULL, *pcur;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return -EINVAL;
+
+	if (list_empty(head))
+		return 0;
+
+	pdma = pchan->dma;
+	list_for_each(p, head) {
+		pcur = list_entry(p, struct mxs_dma_desc, node);
+		if (prev)
+			prev->cmd.next = mxs_dma_cmd_address(pcur);
+		pcur->flags |= MXS_DMA_DESC_READY;
+		prev = pcur;
+		size++;
+	}
+	pcur = list_first_entry(head, struct mxs_dma_desc, node);
+	prev->cmd.next = mxs_dma_cmd_address(pcur);
+
+	spin_lock_irqsave(&pchan->lock, flags);
+	if (!list_empty(&pchan->active)) {
+		pcur = list_entry(pchan->active.next,
+				  struct mxs_dma_desc, node);
+		prev->cmd.next = mxs_dma_cmd_address(pcur);
+		prev = list_entry(pchan->active.prev,
+				  struct mxs_dma_desc, node);
+		pcur = list_first_entry(head, struct mxs_dma_desc, node);
+		prev->cmd.next = mxs_dma_cmd_address(pcur);
+	}
+	list_splice(head, &pchan->active);
+	pchan->pending_num += size;
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(mxs_dma_desc_add_list);
+
+int mxs_dma_get_cooked(int channel, struct list_head *head)
+{
+	unsigned long flags;
+	struct mxs_dma_chan *pchan;
+	if ((channel < 0) || (channel >= MAX_DMA_CHANNELS))
+		return -EINVAL;
+	pchan = mxs_dma_channels + channel;
+	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+		return -EINVAL;
+
+	if (head == NULL)
+		return 0;
+
+	spin_lock_irqsave(&pchan->lock, flags);
+	list_splice(&pchan->done, head);
+	spin_unlock_irqrestore(&pchan->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_dma_get_cooked);
+
+int mxs_dma_device_register(struct mxs_dma_device *pdev)
+{
+	int i;
+	struct mxs_dma_chan *pchan;
+
+	if (pdev == NULL || !pdev->chan_num)
+		return -EINVAL;
+
+	if ((pdev->chan_base >= MAX_DMA_CHANNELS) ||
+	    ((pdev->chan_base + pdev->chan_num) > MAX_DMA_CHANNELS))
+		return -EINVAL;
+
+	mutex_lock(&mxs_dma_mutex);
+	pchan = mxs_dma_channels + pdev->chan_base;
+	for (i = 0; i < pdev->chan_num; i++, pchan++) {
+		pchan->dma = pdev;
+		pchan->flags = MXS_DMA_FLAGS_VALID;
+	}
+	list_add(&pdev->node, &mxs_dma_devices);
+	mutex_unlock(&mxs_dma_mutex);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_dma_device_register);
+
+static int __init mxs_dma_alignment_setup(char *line)
+{
+	get_option(&line, &mxs_dma_alignment);
+	mxs_dma_alignment = (mxs_dma_alignment + 3) & (~3);
+	mxs_dma_alignment = max(mxs_dma_alignment, MXS_DMA_ALIGNMENT);
+	return 1;
+};
+
+__setup("mxs-dma-alignment=", mxs_dma_alignment_setup);
+
+static int mxs_dmaengine_init(void)
+{
+	mxs_dma_pool = dma_pool_create("mxs_dma", NULL,
+				       sizeof(struct mxs_dma_desc),
+				       mxs_dma_alignment, PAGE_SIZE);
+	if (mxs_dma_pool == NULL)
+		return -ENOMEM;
+	return 0;
+}
+
+subsys_initcall(mxs_dmaengine_init);
+
+#ifdef CONFIG_PROC_FS
+
+static void *mxs_dma_proc_seq_start(struct seq_file *file, loff_t * index)
+{
+	if (*index >= MAX_DMA_CHANNELS)
+		return NULL;
+	return mxs_dma_channels + *index;
+}
+
+static void *mxs_dma_proc_seq_next(struct seq_file *file, void *data,
+				   loff_t *index)
+{
+	if (data == NULL)
+		return NULL;
+
+	if (*index >= MAX_DMA_CHANNELS)
+		return NULL;
+
+	return mxs_dma_channels + (*index)++;
+}
+
+static void mxs_dma_proc_seq_stop(struct seq_file *file, void *data)
+{
+}
+
+static int mxs_dma_proc_seq_show(struct seq_file *file, void *data)
+{
+	int result;
+	struct mxs_dma_chan *pchan = (struct mxs_dma_chan *)data;
+	struct mxs_dma_device *pdev = pchan->dma;
+	result = seq_printf(file, "%s-channel%-d	(%s)\n",
+			    pdev->name,
+			    pchan - mxs_dma_channels,
+			    pchan->name ? pchan->name : "idle");
+	return result;
+}
+
+static const struct seq_operations mxc_dma_proc_seq_ops = {
+	.start = mxs_dma_proc_seq_start,
+	.next = mxs_dma_proc_seq_next,
+	.stop = mxs_dma_proc_seq_stop,
+	.show = mxs_dma_proc_seq_show
+};
+
+static int mxs_dma_proc_open(struct inode *inode, struct file *file)
+{
+	return seq_open(file, &mxc_dma_proc_seq_ops);
+}
+
+static const struct file_operations mxs_dma_proc_info_ops = {
+	.open = mxs_dma_proc_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+};
+
+static int __init mxs_dmaengine_info_init(void)
+{
+	struct proc_dir_entry *res;
+	res = create_proc_entry("dma-engine", 0, NULL);
+	if (!res) {
+		printk(KERN_ERR "Failed to create dma info file \n");
+		return -ENOMEM;
+	}
+	res->proc_fops = &mxs_dma_proc_info_ops;
+	return 0;
+}
+
+late_initcall(mxs_dmaengine_info_init);
+#endif
diff --git a/arch/arm/plat-mxs/gpio.c b/arch/arm/plat-mxs/gpio.c
new file mode 100644
index 000000000000..f12d417b03e9
--- /dev/null
+++ b/arch/arm/plat-mxs/gpio.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+#include <linux/list.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/pinctrl.h>
+
+#if MXS_ARCH_NR_GPIOS % PINS_PER_BANK
+#error "MXS_ARCH_NR_GPIOS must be multipled of PINS_PER_BANK"
+#endif
+
+static struct mxs_gpio_port *mxs_gpios[MXS_ARCH_NR_GPIOS / PINS_PER_BANK];
+
+static inline int mxs_valid_gpio(struct mxs_gpio_port *port)
+{
+	struct mxs_gpio_chip *chip = port->chip;
+
+	if (port->id >= (MXS_ARCH_NR_GPIOS / PINS_PER_BANK))
+		return -EINVAL;
+
+	if (port->irq < 0 && port->child_irq > 0)
+		return -EINVAL;
+	if (chip->get == NULL || chip->set == NULL || chip->set_dir == NULL)
+		return -EINVAL;
+	if (port->child_irq > 0) {
+		if (chip->get_irq_stat == NULL)
+			return -EINVAL;
+		if (chip->mask_irq == NULL || chip->unmask_irq == NULL)
+			return -EINVAL;
+	}
+	return 0;
+}
+
+static int mxs_gpio_request(struct gpio_chip *chip, unsigned int pin)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	return mxs_request_pin(MXS_PIN_ENCODE(port->id, pin),
+			       PIN_GPIO, GPIO_ID_NAME);
+}
+
+static void mxs_gpio_free(struct gpio_chip *chip, unsigned int pin)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	return mxs_release_pin(MXS_PIN_ENCODE(port->id, pin), GPIO_ID_NAME);
+}
+
+static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned int index)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	if (port->child_irq < 0)
+		return -ENXIO;
+	return port->child_irq + index;
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned int index)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	return port->chip->get(port, index);
+}
+
+static void mxs_gpio_set(struct gpio_chip *chip, unsigned int index, int v)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	port->chip->set(port, index, v);
+}
+
+static int mxs_gpio_output(struct gpio_chip *chip, unsigned int index, int v)
+{
+	int ret;
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	ret = port->chip->set_dir(port, index, 0);
+	if (!ret)
+		port->chip->set(port, index, v);
+	return ret;
+}
+
+static int mxs_gpio_input(struct gpio_chip *chip, unsigned int index)
+{
+	struct mxs_gpio_port *port;
+	port = container_of(chip, struct mxs_gpio_port, port);
+	return port->chip->set_dir(port, index, 1);
+}
+
+static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	struct mxs_gpio_port *port = get_irq_data(irq);
+	int gpio_irq = port->child_irq;
+	u32 irq_stat = port->chip->get_irq_stat(port);
+
+	desc->chip->mask(irq);
+
+	while (irq_stat) {
+		if (irq_stat & 1)
+			generic_handle_irq(gpio_irq);
+		gpio_irq++;
+		irq_stat >>= 1;
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+static int mxs_gpio_set_irq_type(unsigned int irq, unsigned int type)
+{
+	struct mxs_gpio_port *port;
+	unsigned int gpio = irq_to_gpio(irq);
+	port = mxs_gpios[GPIO_TO_BANK(gpio)];
+	if (port->child_irq < 0)
+		return -ENXIO;
+	if (port->chip->set_irq_type)
+		return port->chip->set_irq_type(port, GPIO_TO_PINS(gpio), type);
+	return -ENODEV;
+}
+
+static void mxs_gpio_ack_irq(unsigned int irq)
+{
+	struct mxs_gpio_port *port;
+	unsigned int gpio = irq_to_gpio(irq);
+	port = mxs_gpios[GPIO_TO_BANK(gpio)];
+	if (port->child_irq < 0)
+		return;
+	if (port->chip->ack_irq)
+		port->chip->ack_irq(port, GPIO_TO_PINS(gpio));
+}
+
+static void mxs_gpio_mask_irq(unsigned int irq)
+{
+	struct mxs_gpio_port *port;
+	unsigned int gpio = irq_to_gpio(irq);
+	port = mxs_gpios[GPIO_TO_BANK(gpio)];
+	if (port->child_irq < 0)
+		return;
+	port->chip->mask_irq(port, GPIO_TO_PINS(gpio));
+}
+
+static void mxs_gpio_unmask_irq(unsigned int irq)
+{
+	struct mxs_gpio_port *port;
+	unsigned int gpio = irq_to_gpio(irq);
+	port = mxs_gpios[GPIO_TO_BANK(gpio)];
+	if (port->child_irq < 0)
+		return;
+	port->chip->unmask_irq(port, GPIO_TO_PINS(gpio));
+}
+
+static struct irq_chip gpio_irq_chip = {
+	.ack = mxs_gpio_ack_irq,
+	.mask = mxs_gpio_mask_irq,
+	.unmask = mxs_gpio_unmask_irq,
+	.set_type = mxs_gpio_set_irq_type,
+};
+
+int __init mxs_add_gpio_port(struct mxs_gpio_port *port)
+{
+	int i, ret;
+	if (!(port && port->chip))
+		return -EINVAL;
+
+	if (mxs_valid_gpio(port))
+		return -EINVAL;
+
+	if (mxs_gpios[port->id])
+		return -EBUSY;
+
+	mxs_gpios[port->id] = port;
+
+	port->port.base = port->id * PINS_PER_BANK;
+	port->port.ngpio = PINS_PER_BANK;
+	port->port.can_sleep = 1;
+	port->port.exported = 1;
+	port->port.to_irq = mxs_gpio_to_irq;
+	port->port.direction_input = mxs_gpio_input;
+	port->port.direction_output = mxs_gpio_output;
+	port->port.get = mxs_gpio_get;
+	port->port.set = mxs_gpio_set;
+	port->port.request = mxs_gpio_request;
+	port->port.free = mxs_gpio_free;
+	port->port.owner = THIS_MODULE;
+	ret = gpiochip_add(&port->port);
+	if (ret < 0)
+		return ret;
+
+	if (port->child_irq < 0)
+		return 0;
+
+	for (i = 0; i < PINS_PER_BANK; i++) {
+		gpio_irq_chip.mask(port->child_irq + i);
+		set_irq_chip(port->child_irq + i, &gpio_irq_chip);
+		set_irq_handler(port->child_irq + i, handle_level_irq);
+		set_irq_flags(port->child_irq + i, IRQF_VALID);
+	}
+	set_irq_chained_handler(port->irq, mxs_gpio_irq_handler);
+	set_irq_data(port->irq, port);
+	return ret;
+};
diff --git a/arch/arm/plat-mxs/icoll.c b/arch/arm/plat-mxs/icoll.c
new file mode 100644
index 000000000000..ef05e63d3dd1
--- /dev/null
+++ b/arch/arm/plat-mxs/icoll.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+
+#include <mach/hardware.h>
+#include <mach/device.h>
+
+#include "regs-icoll.h"
+
+void __iomem *g_icoll_base;
+
+/*
+ * IRQ handling
+ */
+static void icoll_ack_irq(unsigned int irq)
+{
+	__raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR);
+
+	/* ACK current interrupt */
+	__raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
+		     g_icoll_base + HW_ICOLL_LEVELACK);
+
+	/* Barrier */
+	(void)__raw_readl(g_icoll_base + HW_ICOLL_STAT);
+}
+
+static void icoll_mask_irq(unsigned int irq)
+{
+	__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+		     g_icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq));
+}
+
+static void icoll_unmask_irq(unsigned int irq)
+{
+	__raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+		     g_icoll_base + HW_ICOLL_INTERRUPTn_SET(irq));
+}
+
+static struct irq_chip icoll_chip = {
+	.ack = icoll_ack_irq,
+	.mask = icoll_mask_irq,
+	.unmask = icoll_unmask_irq,
+};
+
+void __init avic_init_irq(void __iomem *base, int nr_irqs)
+{
+	int i;
+	g_icoll_base = base;
+
+	/* Reset icoll */
+	__raw_writel(BM_ICOLL_CTRL_SFTRST, g_icoll_base + HW_ICOLL_CTRL_CLR);
+
+	for (i = 0; i < 100000; i++) {
+		if (!(__raw_readl(g_icoll_base + HW_ICOLL_CTRL) &
+		      BM_ICOLL_CTRL_SFTRST))
+			break;
+		udelay(2);
+	}
+	if (i >= 100000) {
+		printk(KERN_ERR "%s:%d timeout when enableing\n",
+		       __func__, __LINE__);
+		return;
+	}
+	__raw_writel(BM_ICOLL_CTRL_CLKGATE, g_icoll_base + HW_ICOLL_CTRL_CLR);
+
+	for (i = 0; i < nr_irqs; i++) {
+		__raw_writel(0, g_icoll_base + HW_ICOLL_INTERRUPTn(i));
+		set_irq_chip(i, &icoll_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	}
+
+	__raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK
+		     (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0),
+		     g_icoll_base + HW_ICOLL_LEVELACK);
+	__raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK
+		     (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1),
+		     g_icoll_base + HW_ICOLL_LEVELACK);
+	__raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK
+		     (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2),
+		     g_icoll_base + HW_ICOLL_LEVELACK);
+	__raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK
+		     (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3),
+		     g_icoll_base + HW_ICOLL_LEVELACK);
+
+	__raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR);
+	/* Barrier */
+	(void)__raw_readl(g_icoll_base + HW_ICOLL_STAT);
+}
diff --git a/arch/arm/plat-mxs/include/mach/clkdev.h b/arch/arm/plat-mxs/include/mach/clkdev.h
new file mode 100644
index 000000000000..d6a82c8d5782
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/clkdev.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+extern int __clk_get(struct clk *clk);
+extern void __clk_put(struct clk *clk);
+
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/clock.h b/arch/arm/plat-mxs/include/mach/clock.h
new file mode 100644
index 000000000000..4eae0f85e3b7
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/clock.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H
+#define __ASM_ARM_ARCH_CLOCK_H
+
+#ifndef __ASSEMBLER__
+
+#include <linux/list.h>
+#include <asm/clkdev.h>
+
+struct clk {
+	int id;
+	struct clk *parent;
+	struct clk *secondary;
+	unsigned long flags;
+
+	unsigned int ref;
+	unsigned int scale_bits;
+	unsigned int enable_bits;
+	unsigned int bypass_bits;
+	unsigned int busy_bits;
+
+	unsigned int wait:1;
+	unsigned int invert:1;
+
+	void __iomem *enable_reg;
+	void __iomem *scale_reg;
+	void __iomem *bypass_reg;
+	void __iomem *busy_reg;
+
+	/*
+	 * Function ptr to set the clock to a new rate. The rate must match a
+	 * supported rate returned from round_rate. Leave blank if clock is not
+	 * programmable
+	 */
+	int (*set_rate) (struct clk *, unsigned long);
+	/*
+	 * Function ptr to get the clock rate.
+	 */
+	unsigned long (*get_rate) (struct clk *);
+	/*
+	 * Function ptr to round the requested clock rate to the nearest
+	 * supported rate that is less than or equal to the requested rate.
+	 */
+	unsigned long (*round_rate) (struct clk *, unsigned long);
+	/*
+	 * Function ptr to enable the clock. Leave blank if clock can not
+	 * be gated.
+	 */
+	int (*enable) (struct clk *);
+	/*
+	 * Function ptr to disable the clock. Leave blank if clock can not
+	 * be gated.
+	 */
+	void (*disable) (struct clk *);
+	/* Function ptr to set the parent clock of the clock. */
+	int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_get_usecount(struct clk *clk);
+extern int clk_register(struct clk_lookup *lookup);
+extern void clk_unregister(struct clk_lookup *lookup);
+
+static inline int clk_is_busy(struct clk *clk)
+{
+	return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits);
+}
+
+/* Clock flags */
+/* 0 ~ 16 attribute flags */
+#define ALWAYS_ENABLED		(1 << 0)	/* Clock cannot be disabled */
+#define RATE_FIXED		(1 << 1)	/* Fixed clock rate */
+
+/* 16 ~ 23 reservied */
+/* 24 ~ 31 run time flags */
+
+#define CLK_REF_UNIT		0x00010000
+#define CLK_REF_LIMIT		0xFFFF0000
+#define CLK_EN_MASK		0x0000FFFF
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h
new file mode 100644
index 000000000000..2debcc89ffec
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/device.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_DEVICE_H
+#define __ASM_ARM_ARCH_DEVICE_H
+
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include <asm/mach/time.h>
+
+#define MXS_MAX_DEVICES 128
+
+struct mxs_sys_timer {
+	struct sys_timer timer;
+	unsigned char id;
+	unsigned char clk_sel;
+	unsigned char resv[2];
+	int irq;
+	struct clk *clk;
+	void __iomem *base;
+};
+
+struct mxs_dev_lookup {
+	char *name;
+	unsigned long lock;
+	int size;
+	struct platform_device *pdev;
+};
+
+/* Define the Platform special structure for each device type*/
+struct mxs_dma_plat_data {
+	unsigned int burst8:1;
+	unsigned int burst:1;
+	unsigned int chan_base;
+	unsigned int chan_num;
+};
+
+extern void mxs_timer_init(struct mxs_sys_timer *timer);
+
+extern void mxs_nop_release(struct device *dev);
+extern int mxs_add_devices(struct platform_device *, int num, int level);
+extern int mxs_add_device(struct platform_device *, int level);
+extern struct platform_device *mxs_get_device(char *name, int id);
+extern struct mxs_dev_lookup *mxs_get_devices(char *name);
+
+#ifdef CONFIG_MXS_ICOLL
+extern void __init avic_init_irq(void __iomem *base, int nr_irqs);
+#endif
+
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h
new file mode 100644
index 000000000000..7d7ab696f32f
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/dmaengine.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_DMA_H
+#define __ASM_ARM_ARCH_DMA_H
+
+#ifndef ARCH_DMA_PIO_WORDS
+#define DMA_PIO_WORDS	15
+#else
+#define DMA_PIO_WORDS	ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT	8
+
+struct mxs_dma_cmd_bits {
+	unsigned int command:2;
+#define NO_DMA_XFER	0x00
+#define DMA_WRITE	0x01
+#define DMA_READ	0x02
+#define DMA_SENSE	0x03
+
+	unsigned int chain:1;
+	unsigned int irq:1;
+	unsigned int resv:2;
+	unsigned int dec_sem:1;
+	unsigned int wait4end:1;
+	unsigned int halt_on_terminate:1;
+	unsigned int terminate_flush:1;
+	unsigned int resv2:2;
+	unsigned int pio_words:4;
+	unsigned int bytes:16;
+};
+
+struct mxs_dma_cmd {
+	unsigned long next;
+	union {
+		unsigned long data;
+		struct mxs_dma_cmd_bits bits;
+	} cmd;
+	union {
+		unsigned long address;
+		unsigned long alternate;
+	};
+	unsigned long pio_words[DMA_PIO_WORDS];
+};
+
+struct mxs_dma_desc {
+	struct mxs_dma_cmd cmd;
+	unsigned int flags;
+#define MXS_DMA_DESC_READY 0x80000000
+	/* address is desc physcial address */
+	dma_addr_t address;
+	/* buffer address */
+	void *buffer;
+	struct list_head node;
+};
+
+struct mxs_dma_chan {
+	const char *name;
+	unsigned long dev;
+	spinlock_t lock;
+	struct mxs_dma_device *dma;
+	unsigned int flags;
+#define MXS_DMA_FLAGS_IDLE	0x00000000
+#define MXS_DMA_FLAGS_BUSY	0x00000001
+#define MXS_DMA_FLAGS_FREE	0x00000000
+#define MXS_DMA_FLAGS_ALLOCATED	0x00010000
+#define MXS_DMA_FLAGS_VALID	0x80000000
+	unsigned int active_num;
+	unsigned int pending_num;
+	struct list_head active;
+	struct list_head done;
+};
+
+/* dma controller devices */
+struct mxs_dma_device {
+	struct list_head node;
+	const char *name;
+	void __iomem *base;
+	unsigned int chan_base;
+	unsigned int chan_num;
+	unsigned int data;
+	struct platform_device *pdev;
+
+	/* operations */
+	int (*enable) (struct mxs_dma_chan *, unsigned int);
+	void (*disable) (struct mxs_dma_chan *, unsigned int);
+	void (*reset) (struct mxs_dma_device *, unsigned int);
+	void (*freeze) (struct mxs_dma_device *, unsigned int);
+	void (*unfreeze) (struct mxs_dma_device *, unsigned int);
+	int (*read_semaphore) (struct mxs_dma_device *, unsigned int);
+	void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned);
+	void (*enable_irq) (struct mxs_dma_device *, unsigned int, int);
+	int (*irq_is_pending) (struct mxs_dma_device *, unsigned int);
+	void (*ack_irq) (struct mxs_dma_device *, unsigned int);
+
+	void (*set_target) (struct mxs_dma_device *, unsigned int, int);
+};
+
+extern int mxs_dma_device_register(struct mxs_dma_device *pdev);
+
+/* request a dma channel */
+extern int mxs_dma_request(int channel, struct device *dev, const char *name);
+/* Release a dma channel */
+extern void mxs_dma_release(int channel, struct device *dev);
+
+/* Enable dma transfer */
+extern int mxs_dma_enable(int channel);
+
+/*
+ * Disable dma transfer and the desc will be putted into done list
+ * Before calling mxs_dma_release, mxs_dma_get_cooked must called to
+ * take dma desc back.
+ */
+extern void mxs_dma_disable(int channel);
+/* reset dma channel */
+extern void mxs_dma_reset(int channel);
+/* freeze dma channel */
+extern void mxs_dma_freeze(int channel);
+/* unfreeze dma channel */
+extern void mxs_dma_unfreeze(int channel);
+/*
+ * Called to task back the done desc. if head is NULL, they will be
+ * put into done list. And must called mxs_dma_get_cooked to take
+ * them back
+ */
+extern int mxs_dma_cooked(int channel, struct list_head *head);
+
+/* Read the dma semaphore to check if there are pending dma desc */
+extern int mxs_dma_read_semaphore(int channel);
+/* check dma irq is pending */
+extern int mxs_dma_irq_is_pending(int channel);
+/* enable or disable dma irq */
+extern void mxs_dma_enable_irq(int channel, int en);
+/* clear dma irq */
+extern void mxs_dma_ack_irq(int channel);
+
+/* Used to configure channel related device selection:NOUSED in i.MX28 */
+extern void mxs_dma_set_target(int channel, int target);
+
+/* mxs dma utility functions */
+extern struct mxs_dma_desc *mxs_dma_alloc_desc(void);
+extern void mxs_dma_free_desc(struct mxs_dma_desc *);
+
+static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
+{
+	return desc->address += offsetof(struct mxs_dma_desc, cmd);
+}
+
+static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc)
+{
+	return pdesc->flags & MXS_DMA_DESC_READY;
+}
+
+/* Add a dma desc to channel*/
+extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+/* Add a list of dma desc to channel*/
+extern int mxs_dma_desc_add_list(int channel, struct list_head *head);
+/* Take the working done desc back */
+extern int mxs_dma_get_cooked(int channel, struct list_head *head);
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/entry-macro.S b/arch/arm/plat-mxs/include/mach/entry-macro.S
new file mode 100644
index 000000000000..353a7b2cc8fd
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/entry-macro.S
@@ -0,0 +1,36 @@
+/*
+ * Low-level IRQ helper macros for Freescale MXS-based
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr \base, =g_icoll_base
+	ldr \base, [\base]
+	ldr \irqnr, [\base, #0x70]
+	cmp \irqnr, #0x7F
+	moveqs \irqnr, #0
+	.endm
+
+	.macro  get_irqnr_preamble, base, tmp
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
diff --git a/arch/arm/plat-mxs/include/mach/gpio.h b/arch/arm/plat-mxs/include/mach/gpio.h
new file mode 100644
index 000000000000..7b634149ec23
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/gpio.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <mach/hardware.h>
+#include <asm-generic/gpio.h>
+
+#define	GPIO_ID_NAME		"gpio"
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+#define gpio_to_irq		__gpio_to_irq
+#define irq_to_gpio(irq)	((irq) - MXS_GPIO_IRQ_START)
+
+struct mxs_gpio_port;
+struct mxs_gpio_chip {
+	int (*set_dir) (struct mxs_gpio_port *, int, unsigned int);
+	int (*get) (struct mxs_gpio_port *, int);
+	void (*set) (struct mxs_gpio_port *, int, int);
+	unsigned int (*get_irq_stat) (struct mxs_gpio_port *);
+	int (*set_irq_type) (struct mxs_gpio_port *, int, unsigned int);
+	void (*unmask_irq) (struct mxs_gpio_port *, int);
+	void (*mask_irq) (struct mxs_gpio_port *, int);
+	void (*ack_irq) (struct mxs_gpio_port *, int);
+};
+
+struct mxs_gpio_port {
+	int id;
+	int irq;
+	int child_irq;
+	struct mxs_gpio_chip *chip;
+	struct gpio_chip port;
+};
+
+extern int mxs_add_gpio_port(struct mxs_gpio_port *port);
+
+static inline void
+mxs_set_gpio_chip(struct mxs_gpio_port *port, struct mxs_gpio_chip *chip)
+{
+	if (port && chip)
+		port->chip = chip;
+}
+
+#endif /* __ASM_ARCH_GPIO_H__ */
diff --git a/arch/arm/plat-mxs/include/mach/hardware.h b/arch/arm/plat-mxs/include/mach/hardware.h
new file mode 100644
index 000000000000..7fdbd054bf41
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/hardware.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_HARDWARE_H
+#define __ASM_ARM_ARCH_HARDWARE_H
+
+#ifdef CONFIG_ARCH_MX28
+# include <mach/mx28.h>
+# define cpu_is_mx28() 1
+# else
+# define cpu_is_mx28() 0
+#endif
+
+#ifndef MXS_EXTEND_IRQS
+#define MXS_EXTEND_IRQS	0
+#endif
+
+#ifndef MXS_ARCH_NR_GPIOS
+#define MXS_ARCH_NR_GPIOS	160
+#endif
+
+#ifndef MXS_EXTEND_NR_GPIOS
+#define MXS_EXTEND_NR_GPIOS	0
+#endif
+
+#define ARCH_NR_GPIOS	(MXS_ARCH_NR_GPIOS + MXS_EXTEND_NR_GPIOS)
+
+#define MXS_GPIO_IRQ_START	ARCH_NR_IRQS
+#define MXS_EXTEND_IRQ_START	(ARCH_NR_IRQS + ARCH_NR_GPIOS)
+
+#endif /* __ASM_ARM_ARCH_HARDWARE_H */
diff --git a/arch/arm/plat-mxs/include/mach/io.h b/arch/arm/plat-mxs/include/mach/io.h
new file mode 100644
index 000000000000..7dff55ef7f12
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a) 	__typesafe_io(a)
+#define __mem_pci(a)	(a)
+#define __mem_isa(a)	(a)
+
+#define SET_REGISTER	0x4
+#define CLR_REGISTER	0x8
+#define TOG_REGISTER	0xC
+
+struct mxs_io_bank {
+	unsigned int raw;
+	unsigned int set;
+	unsigned int clr;
+	unsigned int tog;
+};
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/irqs.h b/arch/arm/plat-mxs/include/mach/irqs.h
new file mode 100644
index 000000000000..f2de0d22ad41
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/irqs.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H__
+#define __ASM_ARCH_IRQS_H__
+
+#include <mach/hardware.h>
+
+#define NR_IRQS	(ARCH_NR_IRQS + ARCH_NR_GPIOS + MXS_EXTEND_IRQS)
+
+#ifndef __ASSEMBLY__
+struct irq_ic_info {
+	unsigned int id_val;
+	unsigned int id_mask;
+	const char *name;
+	unsigned int base;
+};
+
+#define __irq_ic_info_attr __attribute__((__section__(".irq_ic_info.array")))
+
+extern struct irq_ic_info *current_irq_ic_info;
+#endif
+#endif /* __ASM_ARCH_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxs/include/mach/memory.h b/arch/arm/plat-mxs/include/mach/memory.h
new file mode 100644
index 000000000000..79c86db78d49
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/memory.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/page.h>
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET	UL(0x40000000)
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_DMA_ZONE_SIZE
+#define MXS_DMA_ZONE_SIZE	((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT)
+#else
+#define MXS_DMA_ZONE_SIZE	((12 * SZ_1M) >> PAGE_SHIFT)
+#endif
+
+static inline void __arch_adjust_zones(int node, unsigned long *zone_size,
+				       unsigned long *zhole_size)
+{
+	if (node != 0)
+		return;
+	/* Create separate zone to reserve memory for DMA */
+	zone_size[1] = zone_size[0] - MXS_DMA_ZONE_SIZE;
+	zone_size[0] = MXS_DMA_ZONE_SIZE;
+	zhole_size[1] = zhole_size[0];
+	zhole_size[0] = 0;
+}
+
+#define arch_adjust_zones(node, size, holes) \
+	__arch_adjust_zones(node, size, holes)
+
+#endif
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *		address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *		to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)	 __virt_to_phys(x)
+#define __bus_to_virt(x)	 __phys_to_virt(x)
+
+#define ISA_DMA_THRESHOLD	(0x0003ffffULL)
+
+#define CONSISTENT_DMA_SIZE	SZ_32M
+
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/pinctrl.h b/arch/arm/plat-mxs/include/mach/pinctrl.h
new file mode 100644
index 000000000000..3299e4280b90
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/pinctrl.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_ARCH_PINCTRL_H
+#define __ASM_ARM_ARCH_PINCTRL_H
+
+#include <linux/types.h>
+#include <linux/gpio.h>
+
+#define PINS_PER_BANK		32
+#define GPIO_TO_PINS(gpio)	((gpio) % 32)
+#define GPIO_TO_BANK(gpio)	((gpio) / 32)
+
+#define MXS_PIN_TO_GPIO(p)	(((p) & MXS_PIN_PINID_MAX) |\
+				 ((((p) >> MXS_PIN_BANK_BIT) &\
+				 MXS_PIN_BANK_MAX) * PINS_PER_BANK))
+
+#define MXS_PIN_BANK_BIT	24
+#define MXS_PIN_BANK_MAX	(0x7FFFFFFF >> (MXS_PIN_BANK_BIT - 1))
+#define MXS_PIN_PINID_MAX	((1 << MXS_PIN_BANK_BIT) - 1)
+#define MXS_PIN_TO_BANK(p)	(((p) >> MXS_PIN_BANK_BIT) & MXS_PIN_BANK_MAX)
+#define MXS_PIN_TO_PINID(p)	((p) & MXS_PIN_PINID_MAX)
+
+#define MXS_PIN_ENCODE(b, p)	\
+		((((b) & MXS_PIN_BANK_MAX) << MXS_PIN_BANK_BIT) |\
+		 ((p) & MXS_PIN_PINID_MAX))
+
+#define MXS_GPIO_MASK		0x7FFFFFFF
+#define MXS_NON_GPIO		0x80000000
+/*
+ * Each pin may be routed up to four different HW interfaces
+ * including GPIO
+ */
+enum pin_fun {
+	PIN_FUN1 = 0,
+	PIN_FUN2,
+	PIN_FUN3,
+	PIN_GPIO,
+};
+
+/*
+ * Each pin may have different output drive strength in range from
+ * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
+ */
+enum pad_strength {
+	PAD_4MA = 0,
+	PAD_8MA,
+	PAD_12MA,
+	PAD_RESV,
+	PAD_CLEAR = PAD_RESV,
+};
+
+/*
+ * Each pin can be programmed for 1.8V or 3.3V
+ */
+enum pad_voltage {
+	PAD_1_8V = 0,
+	PAD_3_3V,
+};
+
+/*
+ * Structure to define a group of pins and their parameters
+ */
+struct pin_desc {
+	char *name;
+	unsigned int id;
+	enum pin_fun fun;
+	enum pad_strength strength;
+	enum pad_voltage voltage;
+	unsigned pullup:1;
+	unsigned drive:1;
+	unsigned pull:1;
+	unsigned input:1;
+	unsigned data:1;
+};
+
+struct pin_bank {
+	const char *lable[sizeof(long) * 8];
+	unsigned long id;
+	struct pinctrl_chip *chip;
+	unsigned long bitmap;
+	unsigned long gpio_port;
+};
+
+struct pinctrl_chip {
+	char *name;
+	unsigned int nouse;
+	unsigned int bank_size;
+	struct pin_bank *banks;
+	/* OPS */
+	int (*pin2id) (struct pinctrl_chip *, unsigned int, unsigned int *);
+	unsigned int (*get_gpio) (struct pin_bank *, unsigned int);
+	void (*set_strength) (struct pin_bank *, unsigned int,
+			      enum pad_strength);
+	void (*set_voltage) (struct pin_bank *, unsigned int, enum pad_voltage);
+	void (*set_pullup) (struct pin_bank *, unsigned int, int);
+	void (*set_type) (struct pin_bank *, unsigned int, enum pin_fun);
+};
+
+extern int __init mxs_set_pinctrl_chip(struct pinctrl_chip *);
+
+extern unsigned int mxs_pin2gpio(unsigned int);
+extern int mxs_request_pin(unsigned int, enum pin_fun, const char *);
+extern int mxs_set_type(unsigned int, enum pin_fun, const char *);
+extern int mxs_set_strength(unsigned int, enum pad_strength, const char *);
+extern int mxs_set_voltage(unsigned int, enum pad_voltage, const char *);
+extern int mxs_set_pullup(unsigned int, int, const char *);
+extern void mxs_release_pin(unsigned int, const char *);
+#endif
diff --git a/arch/arm/plat-mxs/include/mach/system.h b/arch/arm/plat-mxs/include/mach/system.h
new file mode 100644
index 000000000000..d777723fedf3
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/system.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H__
+#define __ASM_ARCH_SYSTEM_H__
+
+extern void arch_idle(void);
+
+void arch_reset(char mode, const char *cmd);
+int mxs_reset_block(void __iomem *hwreg, int just_enable);
+
+#endif /* __ASM_ARCH_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h
new file mode 100644
index 000000000000..9db3d688223a
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/timex.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*
+ * System time clock is sourced from the 32k clock
+ */
+#define CLOCK_TICK_RATE		32768
diff --git a/arch/arm/plat-mxs/include/mach/uncompress.h b/arch/arm/plat-mxs/include/mach/uncompress.h
new file mode 100644
index 000000000000..fd4e4f845472
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/uncompress.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+
+#include <mach/hardware.h>
+
+/*
+ * Register includes are for when the MMU enabled; we need to define our
+ * own stuff here for pre-MMU use
+ */
+#define UART_PORT_BASE		DUART_PHYS_ADDR
+#define UART(c)			(((volatile unsigned *)UART_PORT_BASE)[c])
+
+/*
+ * This does not append a newline
+ */
+static void putc(char c)
+{
+	/* Wait for TX fifo empty */
+	while ((UART(6) & (1 << 7)) == 0)
+		continue;
+
+	/* Write byte */
+	UART(0) = c;
+
+	/* Wait for last bit to exit the UART */
+	while (UART(6) & (1 << 3))
+		continue;
+}
+
+#define flush()	do { } while (0)
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-mxs/include/mach/vmalloc.h b/arch/arm/plat-mxs/include/mach/vmalloc.h
new file mode 100644
index 000000000000..cc6d5cf3133a
--- /dev/null
+++ b/arch/arm/plat-mxs/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#define VMALLOC_END       (0xF0000000)
diff --git a/arch/arm/plat-mxs/pinctrl.c b/arch/arm/plat-mxs/pinctrl.c
new file mode 100644
index 000000000000..658aa059fca4
--- /dev/null
+++ b/arch/arm/plat-mxs/pinctrl.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <mach/pinctrl.h>
+
+static struct pinctrl_chip *g_chip;
+
+int mxs_request_pin(unsigned int pin, enum pin_fun fun, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+	if (test_and_set_bit(index, &pb->bitmap))
+		return -EBUSY;
+	pb->lable[index] = lab;
+	if (g_chip->set_type)
+		g_chip->set_type(pb, index, fun);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_request_pin);
+
+int mxs_set_type(unsigned int pin, enum pin_fun fun, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+
+	if (!test_bit(index, &pb->bitmap))
+		return -ENOLCK;
+	if (lab != pb->lable[index])	/* lable is const string */
+		return -EINVAL;
+	if (g_chip->set_type)
+		g_chip->set_type(pb, index, fun);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_set_type);
+
+int mxs_set_strength(unsigned int pin, enum pad_strength cfg, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+
+	if (!test_bit(index, &pb->bitmap))
+		return -ENOLCK;
+	if (lab != pb->lable[index])	/* lable is const string */
+		return -EINVAL;
+	if (g_chip->set_strength)
+		g_chip->set_strength(pb, index, cfg);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_set_strength);
+
+int mxs_set_voltage(unsigned int pin, enum pad_voltage cfg, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+
+	if (!test_bit(index, &pb->bitmap))
+		return -ENOLCK;
+	if (lab != pb->lable[index])	/* lable is const string */
+		return -EINVAL;
+	if (g_chip->set_voltage)
+		g_chip->set_voltage(pb, index, cfg);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_set_voltage);
+
+int mxs_set_pullup(unsigned int pin, int en, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+
+	if (!test_bit(index, &pb->bitmap))
+		return -ENOLCK;
+	if (lab != pb->lable[index])	/* lable is const string */
+		return -EINVAL;
+	if (g_chip->set_pullup)
+		g_chip->set_pullup(pb, index, en);
+	return 0;
+}
+EXPORT_SYMBOL(mxs_set_pullup);
+
+void mxs_release_pin(unsigned int pin, const char *lab)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return;
+
+	pb = g_chip->banks + bank;
+
+	if (!test_bit(index, &pb->bitmap))
+		return;
+	if (lab != pb->lable[index])	/* lable is const string */
+		return;
+	pb->lable[index] = NULL;
+
+	clear_bit(index, &pb->bitmap);
+}
+EXPORT_SYMBOL(mxs_release_pin);
+
+unsigned int mxs_pin2gpio(unsigned int pin)
+{
+	int bank, index;
+	struct pin_bank *pb;
+	if (g_chip == NULL)
+		return -ENODEV;
+
+	if (!g_chip->get_gpio)
+		return -ENODEV;
+
+	bank = g_chip->pin2id(g_chip, pin, &index);
+	if (bank < 0 || index < 0 || bank >= g_chip->bank_size)
+		return -EFAULT;
+
+	pb = g_chip->banks + bank;
+
+	return g_chip->get_gpio(pb, index);
+}
+
+int __init mxs_set_pinctrl_chip(struct pinctrl_chip *chip)
+{
+	if (!(chip && chip->banks && chip->bank_size &&
+	      chip->get_gpio && chip->pin2id))
+		return -EINVAL;
+
+	if (g_chip)
+		return -EEXIST;
+	g_chip = chip;
+	return 0;
+};
diff --git a/arch/arm/plat-mxs/regs-apbh.h b/arch/arm/plat-mxs/regs-apbh.h
new file mode 100644
index 000000000000..23f26ca10e9e
--- /dev/null
+++ b/arch/arm/plat-mxs/regs-apbh.h
@@ -0,0 +1,535 @@
+/*
+ * Freescale APBH Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.57
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___APBH_H
+#define __ARCH_ARM___APBH_H
+
+#define HW_APBH_CTRL0	(0x00000000)
+#define HW_APBH_CTRL0_SET	(0x00000004)
+#define HW_APBH_CTRL0_CLR	(0x00000008)
+#define HW_APBH_CTRL0_TOG	(0x0000000c)
+
+#define BM_APBH_CTRL0_SFTRST	0x80000000
+#define BM_APBH_CTRL0_CLKGATE	0x40000000
+#define BM_APBH_CTRL0_AHB_BURST8_EN	0x20000000
+#define BM_APBH_CTRL0_APB_BURST_EN	0x10000000
+#define BP_APBH_CTRL0_RSVD0	16
+#define BM_APBH_CTRL0_RSVD0	0x0FFF0000
+#define BF_APBH_CTRL0_RSVD0(v)  \
+		(((v) << 16) & BM_APBH_CTRL0_RSVD0)
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL	0
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL	0x0000FFFF
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v)  \
+		(((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL)
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0  0x0001
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1  0x0002
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2  0x0004
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3  0x0008
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000
+
+#define HW_APBH_CTRL1	(0x00000010)
+#define HW_APBH_CTRL1_SET	(0x00000014)
+#define HW_APBH_CTRL1_CLR	(0x00000018)
+#define HW_APBH_CTRL1_TOG	(0x0000001c)
+
+#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN	0x80000000
+#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN	0x40000000
+#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN	0x20000000
+#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN	0x10000000
+#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN	0x08000000
+#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN	0x04000000
+#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN	0x02000000
+#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN	0x01000000
+#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN	0x00800000
+#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN	0x00400000
+#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN	0x00200000
+#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN	0x00100000
+#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN	0x00080000
+#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN	0x00040000
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN	0x00020000
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN	0x00010000
+#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ	0x00008000
+#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ	0x00004000
+#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ	0x00002000
+#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ	0x00001000
+#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ	0x00000800
+#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ	0x00000400
+#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ	0x00000200
+#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ	0x00000100
+#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ	0x00000080
+#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ	0x00000040
+#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ	0x00000020
+#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ	0x00000010
+#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ	0x00000008
+#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ	0x00000004
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ	0x00000002
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ	0x00000001
+
+#define HW_APBH_CTRL2	(0x00000020)
+#define HW_APBH_CTRL2_SET	(0x00000024)
+#define HW_APBH_CTRL2_CLR	(0x00000028)
+#define HW_APBH_CTRL2_TOG	(0x0000002c)
+
+#define BM_APBH_CTRL2_CH15_ERROR_STATUS	0x80000000
+#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH14_ERROR_STATUS	0x40000000
+#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH13_ERROR_STATUS	0x20000000
+#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH12_ERROR_STATUS	0x10000000
+#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH11_ERROR_STATUS	0x08000000
+#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH10_ERROR_STATUS	0x04000000
+#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH9_ERROR_STATUS	0x02000000
+#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH8_ERROR_STATUS	0x01000000
+#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH7_ERROR_STATUS	0x00800000
+#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH6_ERROR_STATUS	0x00400000
+#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH5_ERROR_STATUS	0x00200000
+#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH4_ERROR_STATUS	0x00100000
+#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH3_ERROR_STATUS	0x00080000
+#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH2_ERROR_STATUS	0x00040000
+#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH1_ERROR_STATUS	0x00020000
+#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH0_ERROR_STATUS	0x00010000
+#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBH_CTRL2_CH15_ERROR_IRQ	0x00008000
+#define BM_APBH_CTRL2_CH14_ERROR_IRQ	0x00004000
+#define BM_APBH_CTRL2_CH13_ERROR_IRQ	0x00002000
+#define BM_APBH_CTRL2_CH12_ERROR_IRQ	0x00001000
+#define BM_APBH_CTRL2_CH11_ERROR_IRQ	0x00000800
+#define BM_APBH_CTRL2_CH10_ERROR_IRQ	0x00000400
+#define BM_APBH_CTRL2_CH9_ERROR_IRQ	0x00000200
+#define BM_APBH_CTRL2_CH8_ERROR_IRQ	0x00000100
+#define BM_APBH_CTRL2_CH7_ERROR_IRQ	0x00000080
+#define BM_APBH_CTRL2_CH6_ERROR_IRQ	0x00000040
+#define BM_APBH_CTRL2_CH5_ERROR_IRQ	0x00000020
+#define BM_APBH_CTRL2_CH4_ERROR_IRQ	0x00000010
+#define BM_APBH_CTRL2_CH3_ERROR_IRQ	0x00000008
+#define BM_APBH_CTRL2_CH2_ERROR_IRQ	0x00000004
+#define BM_APBH_CTRL2_CH1_ERROR_IRQ	0x00000002
+#define BM_APBH_CTRL2_CH0_ERROR_IRQ	0x00000001
+
+#define HW_APBH_CHANNEL_CTRL	(0x00000030)
+#define HW_APBH_CHANNEL_CTRL_SET	(0x00000034)
+#define HW_APBH_CHANNEL_CTRL_CLR	(0x00000038)
+#define HW_APBH_CHANNEL_CTRL_TOG	(0x0000003c)
+
+#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL	16
+#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL	0xFFFF0000
+#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \
+		(((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL)
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0  0x0001
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1  0x0002
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2  0x0004
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3  0x0008
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000
+#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000
+#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL	0
+#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL	0x0000FFFF
+#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v)  \
+		(((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL)
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0  0x0001
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1  0x0002
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2  0x0004
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3  0x0008
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000
+#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000
+
+#define HW_APBH_DEVSEL	(0x00000040)
+
+#define BP_APBH_DEVSEL_CH15	30
+#define BM_APBH_DEVSEL_CH15	0xC0000000
+#define BF_APBH_DEVSEL_CH15(v) \
+		(((v) << 30) & BM_APBH_DEVSEL_CH15)
+#define BP_APBH_DEVSEL_CH14	28
+#define BM_APBH_DEVSEL_CH14	0x30000000
+#define BF_APBH_DEVSEL_CH14(v)  \
+		(((v) << 28) & BM_APBH_DEVSEL_CH14)
+#define BP_APBH_DEVSEL_CH13	26
+#define BM_APBH_DEVSEL_CH13	0x0C000000
+#define BF_APBH_DEVSEL_CH13(v)  \
+		(((v) << 26) & BM_APBH_DEVSEL_CH13)
+#define BP_APBH_DEVSEL_CH12	24
+#define BM_APBH_DEVSEL_CH12	0x03000000
+#define BF_APBH_DEVSEL_CH12(v)  \
+		(((v) << 24) & BM_APBH_DEVSEL_CH12)
+#define BP_APBH_DEVSEL_CH11	22
+#define BM_APBH_DEVSEL_CH11	0x00C00000
+#define BF_APBH_DEVSEL_CH11(v)  \
+		(((v) << 22) & BM_APBH_DEVSEL_CH11)
+#define BP_APBH_DEVSEL_CH10	20
+#define BM_APBH_DEVSEL_CH10	0x00300000
+#define BF_APBH_DEVSEL_CH10(v)  \
+		(((v) << 20) & BM_APBH_DEVSEL_CH10)
+#define BP_APBH_DEVSEL_CH9	18
+#define BM_APBH_DEVSEL_CH9	0x000C0000
+#define BF_APBH_DEVSEL_CH9(v)  \
+		(((v) << 18) & BM_APBH_DEVSEL_CH9)
+#define BP_APBH_DEVSEL_CH8	16
+#define BM_APBH_DEVSEL_CH8	0x00030000
+#define BF_APBH_DEVSEL_CH8(v)  \
+		(((v) << 16) & BM_APBH_DEVSEL_CH8)
+#define BP_APBH_DEVSEL_CH7	14
+#define BM_APBH_DEVSEL_CH7	0x0000C000
+#define BF_APBH_DEVSEL_CH7(v)  \
+		(((v) << 14) & BM_APBH_DEVSEL_CH7)
+#define BP_APBH_DEVSEL_CH6	12
+#define BM_APBH_DEVSEL_CH6	0x00003000
+#define BF_APBH_DEVSEL_CH6(v)  \
+		(((v) << 12) & BM_APBH_DEVSEL_CH6)
+#define BP_APBH_DEVSEL_CH5	10
+#define BM_APBH_DEVSEL_CH5	0x00000C00
+#define BF_APBH_DEVSEL_CH5(v)  \
+		(((v) << 10) & BM_APBH_DEVSEL_CH5)
+#define BP_APBH_DEVSEL_CH4	8
+#define BM_APBH_DEVSEL_CH4	0x00000300
+#define BF_APBH_DEVSEL_CH4(v)  \
+		(((v) << 8) & BM_APBH_DEVSEL_CH4)
+#define BP_APBH_DEVSEL_CH3	6
+#define BM_APBH_DEVSEL_CH3	0x000000C0
+#define BF_APBH_DEVSEL_CH3(v)  \
+		(((v) << 6) & BM_APBH_DEVSEL_CH3)
+#define BP_APBH_DEVSEL_CH2	4
+#define BM_APBH_DEVSEL_CH2	0x00000030
+#define BF_APBH_DEVSEL_CH2(v)  \
+		(((v) << 4) & BM_APBH_DEVSEL_CH2)
+#define BP_APBH_DEVSEL_CH1	2
+#define BM_APBH_DEVSEL_CH1	0x0000000C
+#define BF_APBH_DEVSEL_CH1(v)  \
+		(((v) << 2) & BM_APBH_DEVSEL_CH1)
+#define BP_APBH_DEVSEL_CH0	0
+#define BM_APBH_DEVSEL_CH0	0x00000003
+#define BF_APBH_DEVSEL_CH0(v)  \
+		(((v) << 0) & BM_APBH_DEVSEL_CH0)
+
+#define HW_APBH_DMA_BURST_SIZE	(0x00000050)
+
+#define BP_APBH_DMA_BURST_SIZE_CH15	30
+#define BM_APBH_DMA_BURST_SIZE_CH15	0xC0000000
+#define BF_APBH_DMA_BURST_SIZE_CH15(v) \
+		(((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15)
+#define BP_APBH_DMA_BURST_SIZE_CH14	28
+#define BM_APBH_DMA_BURST_SIZE_CH14	0x30000000
+#define BF_APBH_DMA_BURST_SIZE_CH14(v)  \
+		(((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14)
+#define BP_APBH_DMA_BURST_SIZE_CH13	26
+#define BM_APBH_DMA_BURST_SIZE_CH13	0x0C000000
+#define BF_APBH_DMA_BURST_SIZE_CH13(v)  \
+		(((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13)
+#define BP_APBH_DMA_BURST_SIZE_CH12	24
+#define BM_APBH_DMA_BURST_SIZE_CH12	0x03000000
+#define BF_APBH_DMA_BURST_SIZE_CH12(v)  \
+		(((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12)
+#define BP_APBH_DMA_BURST_SIZE_CH11	22
+#define BM_APBH_DMA_BURST_SIZE_CH11	0x00C00000
+#define BF_APBH_DMA_BURST_SIZE_CH11(v)  \
+		(((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11)
+#define BP_APBH_DMA_BURST_SIZE_CH10	20
+#define BM_APBH_DMA_BURST_SIZE_CH10	0x00300000
+#define BF_APBH_DMA_BURST_SIZE_CH10(v)  \
+		(((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10)
+#define BP_APBH_DMA_BURST_SIZE_CH9	18
+#define BM_APBH_DMA_BURST_SIZE_CH9	0x000C0000
+#define BF_APBH_DMA_BURST_SIZE_CH9(v)  \
+		(((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9)
+#define BP_APBH_DMA_BURST_SIZE_CH8	16
+#define BM_APBH_DMA_BURST_SIZE_CH8	0x00030000
+#define BF_APBH_DMA_BURST_SIZE_CH8(v)  \
+		(((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8)
+#define BP_APBH_DMA_BURST_SIZE_CH7	14
+#define BM_APBH_DMA_BURST_SIZE_CH7	0x0000C000
+#define BF_APBH_DMA_BURST_SIZE_CH7(v)  \
+		(((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7)
+#define BP_APBH_DMA_BURST_SIZE_CH6	12
+#define BM_APBH_DMA_BURST_SIZE_CH6	0x00003000
+#define BF_APBH_DMA_BURST_SIZE_CH6(v)  \
+		(((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6)
+#define BP_APBH_DMA_BURST_SIZE_CH5	10
+#define BM_APBH_DMA_BURST_SIZE_CH5	0x00000C00
+#define BF_APBH_DMA_BURST_SIZE_CH5(v)  \
+		(((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5)
+#define BP_APBH_DMA_BURST_SIZE_CH4	8
+#define BM_APBH_DMA_BURST_SIZE_CH4	0x00000300
+#define BF_APBH_DMA_BURST_SIZE_CH4(v)  \
+		(((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4)
+#define BP_APBH_DMA_BURST_SIZE_CH3	6
+#define BM_APBH_DMA_BURST_SIZE_CH3	0x000000C0
+#define BF_APBH_DMA_BURST_SIZE_CH3(v)  \
+		(((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3)
+#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0
+#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1
+#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2
+#define BP_APBH_DMA_BURST_SIZE_CH2	4
+#define BM_APBH_DMA_BURST_SIZE_CH2	0x00000030
+#define BF_APBH_DMA_BURST_SIZE_CH2(v)  \
+		(((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2)
+#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0
+#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1
+#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2
+#define BP_APBH_DMA_BURST_SIZE_CH1	2
+#define BM_APBH_DMA_BURST_SIZE_CH1	0x0000000C
+#define BF_APBH_DMA_BURST_SIZE_CH1(v)  \
+		(((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1)
+#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0
+#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1
+#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2
+#define BP_APBH_DMA_BURST_SIZE_CH0	0
+#define BM_APBH_DMA_BURST_SIZE_CH0	0x00000003
+#define BF_APBH_DMA_BURST_SIZE_CH0(v)  \
+		(((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0)
+#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0
+#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1
+#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2
+
+#define HW_APBH_DEBUG	(0x00000060)
+
+#define BP_APBH_DEBUG_RSVD	1
+#define BM_APBH_DEBUG_RSVD	0xFFFFFFFE
+#define BF_APBH_DEBUG_RSVD(v) \
+		(((v) << 1) & BM_APBH_DEBUG_RSVD)
+#define BM_APBH_DEBUG_GPMI_ONE_FIFO	0x00000001
+
+/*
+ *  multi-register-define name HW_APBH_CHn_CURCMDAR
+ *              base 0x00000100
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_CURCMDAR(n)	(0x00000100 + (n) * 0x70)
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR	0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR	0xFFFFFFFF
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBH_CHn_NXTCMDAR
+ *              base 0x00000110
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_NXTCMDAR(n)	(0x00000110 + (n) * 0x70)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR	0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR	0xFFFFFFFF
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBH_CHn_CMD
+ *              base 0x00000120
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_CMD(n)	(0x00000120 + (n) * 0x70)
+#define BP_APBH_CHn_CMD_XFER_COUNT	16
+#define BM_APBH_CHn_CMD_XFER_COUNT	0xFFFF0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
+		(((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT)
+#define BP_APBH_CHn_CMD_CMDWORDS	12
+#define BM_APBH_CHn_CMD_CMDWORDS	0x0000F000
+#define BF_APBH_CHn_CMD_CMDWORDS(v)  \
+		(((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS)
+#define BP_APBH_CHn_CMD_RSVD1	9
+#define BM_APBH_CHn_CMD_RSVD1	0x00000E00
+#define BF_APBH_CHn_CMD_RSVD1(v)  \
+		(((v) << 9) & BM_APBH_CHn_CMD_RSVD1)
+#define BM_APBH_CHn_CMD_HALTONTERMINATE	0x00000100
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD	0x00000080
+#define BM_APBH_CHn_CMD_SEMAPHORE	0x00000040
+#define BM_APBH_CHn_CMD_NANDWAIT4READY	0x00000020
+#define BM_APBH_CHn_CMD_NANDLOCK	0x00000010
+#define BM_APBH_CHn_CMD_IRQONCMPLT	0x00000008
+#define BM_APBH_CHn_CMD_CHAIN	0x00000004
+#define BP_APBH_CHn_CMD_COMMAND	0
+#define BM_APBH_CHn_CMD_COMMAND	0x00000003
+#define BF_APBH_CHn_CMD_COMMAND(v)  \
+		(((v) << 0) & BM_APBH_CHn_CMD_COMMAND)
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE   0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ    0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE   0x3
+
+/*
+ *  multi-register-define name HW_APBH_CHn_BAR
+ *              base 0x00000130
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_BAR(n)	(0x00000130 + (n) * 0x70)
+#define BP_APBH_CHn_BAR_ADDRESS	0
+#define BM_APBH_CHn_BAR_ADDRESS	0xFFFFFFFF
+#define BF_APBH_CHn_BAR_ADDRESS(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBH_CHn_SEMA
+ *              base 0x00000140
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_SEMA(n)	(0x00000140 + (n) * 0x70)
+#define BP_APBH_CHn_SEMA_RSVD2	24
+#define BM_APBH_CHn_SEMA_RSVD2	0xFF000000
+#define BF_APBH_CHn_SEMA_RSVD2(v) \
+		(((v) << 24) & BM_APBH_CHn_SEMA_RSVD2)
+#define BP_APBH_CHn_SEMA_PHORE	16
+#define BM_APBH_CHn_SEMA_PHORE	0x00FF0000
+#define BF_APBH_CHn_SEMA_PHORE(v)  \
+		(((v) << 16) & BM_APBH_CHn_SEMA_PHORE)
+#define BP_APBH_CHn_SEMA_RSVD1	8
+#define BM_APBH_CHn_SEMA_RSVD1	0x0000FF00
+#define BF_APBH_CHn_SEMA_RSVD1(v)  \
+		(((v) << 8) & BM_APBH_CHn_SEMA_RSVD1)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA	0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA	0x000000FF
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)  \
+		(((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA)
+
+/*
+ *  multi-register-define name HW_APBH_CHn_DEBUG1
+ *              base 0x00000150
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_DEBUG1(n)	(0x00000150 + (n) * 0x70)
+#define BM_APBH_CHn_DEBUG1_REQ	0x80000000
+#define BM_APBH_CHn_DEBUG1_BURST	0x40000000
+#define BM_APBH_CHn_DEBUG1_KICK	0x20000000
+#define BM_APBH_CHn_DEBUG1_END	0x10000000
+#define BM_APBH_CHn_DEBUG1_SENSE	0x08000000
+#define BM_APBH_CHn_DEBUG1_READY	0x04000000
+#define BM_APBH_CHn_DEBUG1_LOCK	0x02000000
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID	0x01000000
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY	0x00800000
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL	0x00400000
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY	0x00200000
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL	0x00100000
+#define BP_APBH_CHn_DEBUG1_RSVD1	5
+#define BM_APBH_CHn_DEBUG1_RSVD1	0x000FFFE0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v)  \
+		(((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1)
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE	0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE	0x0000001F
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v)  \
+		(((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE)
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE            0x00
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1        0x01
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3        0x02
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2        0x03
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE     0x04
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT        0x05
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4        0x06
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ         0x07
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH      0x08
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT       0x09
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE           0x0C
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ        0x0D
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN     0x0E
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE   0x0F
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE       0x14
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END        0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT      0x1C
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT      0x1E
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY      0x1F
+
+/*
+ *  multi-register-define name HW_APBH_CHn_DEBUG2
+ *              base 0x00000160
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBH_CHn_DEBUG2(n)	(0x00000160 + (n) * 0x70)
+#define BP_APBH_CHn_DEBUG2_APB_BYTES	16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES	0xFFFF0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \
+		(((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES)
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES	0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES	0x0000FFFF
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v)  \
+		(((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES)
+
+#define HW_APBH_VERSION	(0x00000800)
+
+#define BP_APBH_VERSION_MAJOR	24
+#define BM_APBH_VERSION_MAJOR	0xFF000000
+#define BF_APBH_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_APBH_VERSION_MAJOR)
+#define BP_APBH_VERSION_MINOR	16
+#define BM_APBH_VERSION_MINOR	0x00FF0000
+#define BF_APBH_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_APBH_VERSION_MINOR)
+#define BP_APBH_VERSION_STEP	0
+#define BM_APBH_VERSION_STEP	0x0000FFFF
+#define BF_APBH_VERSION_STEP(v)  \
+		(((v) << 0) & BM_APBH_VERSION_STEP)
+#endif /* __ARCH_ARM___APBH_H */
diff --git a/arch/arm/plat-mxs/regs-apbx.h b/arch/arm/plat-mxs/regs-apbx.h
new file mode 100644
index 000000000000..f788f1303ece
--- /dev/null
+++ b/arch/arm/plat-mxs/regs-apbx.h
@@ -0,0 +1,433 @@
+/*
+ * Freescale APBX Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.30
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___APBX_H
+#define __ARCH_ARM___APBX_H
+
+#define HW_APBX_CTRL0	(0x00000000)
+#define HW_APBX_CTRL0_SET	(0x00000004)
+#define HW_APBX_CTRL0_CLR	(0x00000008)
+#define HW_APBX_CTRL0_TOG	(0x0000000c)
+
+#define BM_APBX_CTRL0_SFTRST	0x80000000
+#define BM_APBX_CTRL0_CLKGATE	0x40000000
+#define BP_APBX_CTRL0_RSVD0	0
+#define BM_APBX_CTRL0_RSVD0	0x3FFFFFFF
+#define BF_APBX_CTRL0_RSVD0(v)  \
+		(((v) << 0) & BM_APBX_CTRL0_RSVD0)
+
+#define HW_APBX_CTRL1	(0x00000010)
+#define HW_APBX_CTRL1_SET	(0x00000014)
+#define HW_APBX_CTRL1_CLR	(0x00000018)
+#define HW_APBX_CTRL1_TOG	(0x0000001c)
+
+#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ_EN	0x80000000
+#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ_EN	0x40000000
+#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ_EN	0x20000000
+#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ_EN	0x10000000
+#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ_EN	0x08000000
+#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ_EN	0x04000000
+#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ_EN	0x02000000
+#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ_EN	0x01000000
+#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN	0x00800000
+#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN	0x00400000
+#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ_EN	0x00200000
+#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ_EN	0x00100000
+#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ_EN	0x00080000
+#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ_EN	0x00040000
+#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ_EN	0x00020000
+#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ_EN	0x00010000
+#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ	0x00008000
+#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ	0x00004000
+#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ	0x00002000
+#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ	0x00001000
+#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ	0x00000800
+#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ	0x00000400
+#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ	0x00000200
+#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ	0x00000100
+#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ	0x00000080
+#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ	0x00000040
+#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ	0x00000020
+#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ	0x00000010
+#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ	0x00000008
+#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ	0x00000004
+#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ	0x00000002
+#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ	0x00000001
+
+#define HW_APBX_CTRL2	(0x00000020)
+#define HW_APBX_CTRL2_SET	(0x00000024)
+#define HW_APBX_CTRL2_CLR	(0x00000028)
+#define HW_APBX_CTRL2_TOG	(0x0000002c)
+
+#define BM_APBX_CTRL2_CH15_ERROR_STATUS	0x80000000
+#define BV_APBX_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH15_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH14_ERROR_STATUS	0x40000000
+#define BV_APBX_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH14_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH13_ERROR_STATUS	0x20000000
+#define BV_APBX_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH13_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH12_ERROR_STATUS	0x10000000
+#define BV_APBX_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH12_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH11_ERROR_STATUS	0x08000000
+#define BV_APBX_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH11_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH10_ERROR_STATUS	0x04000000
+#define BV_APBX_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH10_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH9_ERROR_STATUS	0x02000000
+#define BV_APBX_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH9_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH8_ERROR_STATUS	0x01000000
+#define BV_APBX_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH8_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH7_ERROR_STATUS	0x00800000
+#define BV_APBX_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH7_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH6_ERROR_STATUS	0x00400000
+#define BV_APBX_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH6_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH5_ERROR_STATUS	0x00200000
+#define BV_APBX_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH5_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH4_ERROR_STATUS	0x00100000
+#define BV_APBX_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH4_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH3_ERROR_STATUS	0x00080000
+#define BV_APBX_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH3_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH2_ERROR_STATUS	0x00040000
+#define BV_APBX_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH2_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH1_ERROR_STATUS	0x00020000
+#define BV_APBX_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH1_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH0_ERROR_STATUS	0x00010000
+#define BV_APBX_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBX_CTRL2_CH0_ERROR_STATUS__BUS_ERROR   0x1
+#define BM_APBX_CTRL2_CH15_ERROR_IRQ	0x00008000
+#define BM_APBX_CTRL2_CH14_ERROR_IRQ	0x00004000
+#define BM_APBX_CTRL2_CH13_ERROR_IRQ	0x00002000
+#define BM_APBX_CTRL2_CH12_ERROR_IRQ	0x00001000
+#define BM_APBX_CTRL2_CH11_ERROR_IRQ	0x00000800
+#define BM_APBX_CTRL2_CH10_ERROR_IRQ	0x00000400
+#define BM_APBX_CTRL2_CH9_ERROR_IRQ	0x00000200
+#define BM_APBX_CTRL2_CH8_ERROR_IRQ	0x00000100
+#define BM_APBX_CTRL2_CH7_ERROR_IRQ	0x00000080
+#define BM_APBX_CTRL2_CH6_ERROR_IRQ	0x00000040
+#define BM_APBX_CTRL2_CH5_ERROR_IRQ	0x00000020
+#define BM_APBX_CTRL2_CH4_ERROR_IRQ	0x00000010
+#define BM_APBX_CTRL2_CH3_ERROR_IRQ	0x00000008
+#define BM_APBX_CTRL2_CH2_ERROR_IRQ	0x00000004
+#define BM_APBX_CTRL2_CH1_ERROR_IRQ	0x00000002
+#define BM_APBX_CTRL2_CH0_ERROR_IRQ	0x00000001
+
+#define HW_APBX_CHANNEL_CTRL	(0x00000030)
+#define HW_APBX_CHANNEL_CTRL_SET	(0x00000034)
+#define HW_APBX_CHANNEL_CTRL_CLR	(0x00000038)
+#define HW_APBX_CHANNEL_CTRL_TOG	(0x0000003c)
+
+#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL	16
+#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL	0xFFFF0000
+#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \
+		(((v) << 16) & BM_APBX_CHANNEL_CTRL_RESET_CHANNEL)
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_RX 0x0001
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_TX 0x0002
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x0004
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF0    0x0010
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1    0x0020
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C0     0x0040
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C1     0x0080
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x0100
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x0200
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x0400
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x0800
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_RX 0x1000
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_TX 0x2000
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_RX 0x4000
+#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_TX 0x8000
+#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL	0
+#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL	0x0000FFFF
+#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v)  \
+		(((v) << 0) & BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL)
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_RX 0x0001
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_TX 0x0002
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x0004
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF0    0x0010
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1    0x0020
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C0     0x0040
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C1     0x0080
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x0100
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x0200
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x0400
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x0800
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_RX 0x1000
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_TX 0x2000
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_RX 0x4000
+#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_TX 0x8000
+
+#define HW_APBX_DEVSEL	(0x00000040)
+#define HW_APBX_DEVSEL_SET	(0x00000044)
+#define HW_APBX_DEVSEL_CLR	(0x00000048)
+#define HW_APBX_DEVSEL_TOG	(0x0000004c)
+
+#define BP_APBX_DEVSEL_CH15	30
+#define BM_APBX_DEVSEL_CH15	0xC0000000
+#define BF_APBX_DEVSEL_CH15(v) \
+		(((v) << 30) & BM_APBX_DEVSEL_CH15)
+#define BP_APBX_DEVSEL_CH14	28
+#define BM_APBX_DEVSEL_CH14	0x30000000
+#define BF_APBX_DEVSEL_CH14(v)  \
+		(((v) << 28) & BM_APBX_DEVSEL_CH14)
+#define BP_APBX_DEVSEL_CH13	26
+#define BM_APBX_DEVSEL_CH13	0x0C000000
+#define BF_APBX_DEVSEL_CH13(v)  \
+		(((v) << 26) & BM_APBX_DEVSEL_CH13)
+#define BP_APBX_DEVSEL_CH12	24
+#define BM_APBX_DEVSEL_CH12	0x03000000
+#define BF_APBX_DEVSEL_CH12(v)  \
+		(((v) << 24) & BM_APBX_DEVSEL_CH12)
+#define BP_APBX_DEVSEL_CH11	22
+#define BM_APBX_DEVSEL_CH11	0x00C00000
+#define BF_APBX_DEVSEL_CH11(v)  \
+		(((v) << 22) & BM_APBX_DEVSEL_CH11)
+#define BP_APBX_DEVSEL_CH10	20
+#define BM_APBX_DEVSEL_CH10	0x00300000
+#define BF_APBX_DEVSEL_CH10(v)  \
+		(((v) << 20) & BM_APBX_DEVSEL_CH10)
+#define BP_APBX_DEVSEL_CH9	18
+#define BM_APBX_DEVSEL_CH9	0x000C0000
+#define BF_APBX_DEVSEL_CH9(v)  \
+		(((v) << 18) & BM_APBX_DEVSEL_CH9)
+#define BP_APBX_DEVSEL_CH8	16
+#define BM_APBX_DEVSEL_CH8	0x00030000
+#define BF_APBX_DEVSEL_CH8(v)  \
+		(((v) << 16) & BM_APBX_DEVSEL_CH8)
+#define BP_APBX_DEVSEL_CH7	14
+#define BM_APBX_DEVSEL_CH7	0x0000C000
+#define BF_APBX_DEVSEL_CH7(v)  \
+		(((v) << 14) & BM_APBX_DEVSEL_CH7)
+#define BP_APBX_DEVSEL_CH6	12
+#define BM_APBX_DEVSEL_CH6	0x00003000
+#define BF_APBX_DEVSEL_CH6(v)  \
+		(((v) << 12) & BM_APBX_DEVSEL_CH6)
+#define BP_APBX_DEVSEL_CH5	10
+#define BM_APBX_DEVSEL_CH5	0x00000C00
+#define BF_APBX_DEVSEL_CH5(v)  \
+		(((v) << 10) & BM_APBX_DEVSEL_CH5)
+#define BP_APBX_DEVSEL_CH4	8
+#define BM_APBX_DEVSEL_CH4	0x00000300
+#define BF_APBX_DEVSEL_CH4(v)  \
+		(((v) << 8) & BM_APBX_DEVSEL_CH4)
+#define BP_APBX_DEVSEL_CH3	6
+#define BM_APBX_DEVSEL_CH3	0x000000C0
+#define BF_APBX_DEVSEL_CH3(v)  \
+		(((v) << 6) & BM_APBX_DEVSEL_CH3)
+#define BP_APBX_DEVSEL_CH2	4
+#define BM_APBX_DEVSEL_CH2	0x00000030
+#define BF_APBX_DEVSEL_CH2(v)  \
+		(((v) << 4) & BM_APBX_DEVSEL_CH2)
+#define BP_APBX_DEVSEL_CH1	2
+#define BM_APBX_DEVSEL_CH1	0x0000000C
+#define BF_APBX_DEVSEL_CH1(v)  \
+		(((v) << 2) & BM_APBX_DEVSEL_CH1)
+#define BP_APBX_DEVSEL_CH0	0
+#define BM_APBX_DEVSEL_CH0	0x00000003
+#define BF_APBX_DEVSEL_CH0(v)  \
+		(((v) << 0) & BM_APBX_DEVSEL_CH0)
+
+/*
+ *  multi-register-define name HW_APBX_CHn_CURCMDAR
+ *              base 0x00000100
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_CURCMDAR(n)	(0x00000100 + (n) * 0x70)
+#define BP_APBX_CHn_CURCMDAR_CMD_ADDR	0
+#define BM_APBX_CHn_CURCMDAR_CMD_ADDR	0xFFFFFFFF
+#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBX_CHn_NXTCMDAR
+ *              base 0x00000110
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_NXTCMDAR(n)	(0x00000110 + (n) * 0x70)
+#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR	0
+#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR	0xFFFFFFFF
+#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBX_CHn_CMD
+ *              base 0x00000120
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_CMD(n)	(0x00000120 + (n) * 0x70)
+#define BP_APBX_CHn_CMD_XFER_COUNT	16
+#define BM_APBX_CHn_CMD_XFER_COUNT	0xFFFF0000
+#define BF_APBX_CHn_CMD_XFER_COUNT(v) \
+		(((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT)
+#define BP_APBX_CHn_CMD_CMDWORDS	12
+#define BM_APBX_CHn_CMD_CMDWORDS	0x0000F000
+#define BF_APBX_CHn_CMD_CMDWORDS(v)  \
+		(((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS)
+#define BP_APBX_CHn_CMD_RSVD1	10
+#define BM_APBX_CHn_CMD_RSVD1	0x00000C00
+#define BF_APBX_CHn_CMD_RSVD1(v)  \
+		(((v) << 10) & BM_APBX_CHn_CMD_RSVD1)
+#define BM_APBX_CHn_CMD_TERMINATEFLUSH	0x00000200
+#define BM_APBX_CHn_CMD_HALTONTERMINATE	0x00000100
+#define BM_APBX_CHn_CMD_WAIT4ENDCMD	0x00000080
+#define BM_APBX_CHn_CMD_SEMAPHORE	0x00000040
+#define BP_APBX_CHn_CMD_RSVD0	4
+#define BM_APBX_CHn_CMD_RSVD0	0x00000030
+#define BF_APBX_CHn_CMD_RSVD0(v)  \
+		(((v) << 4) & BM_APBX_CHn_CMD_RSVD0)
+#define BM_APBX_CHn_CMD_IRQONCMPLT	0x00000008
+#define BM_APBX_CHn_CMD_CHAIN	0x00000004
+#define BP_APBX_CHn_CMD_COMMAND	0
+#define BM_APBX_CHn_CMD_COMMAND	0x00000003
+#define BF_APBX_CHn_CMD_COMMAND(v)  \
+		(((v) << 0) & BM_APBX_CHn_CMD_COMMAND)
+#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
+#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE   0x1
+#define BV_APBX_CHn_CMD_COMMAND__DMA_READ    0x2
+
+/*
+ *  multi-register-define name HW_APBX_CHn_BAR
+ *              base 0x00000130
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_BAR(n)	(0x00000130 + (n) * 0x70)
+#define BP_APBX_CHn_BAR_ADDRESS	0
+#define BM_APBX_CHn_BAR_ADDRESS	0xFFFFFFFF
+#define BF_APBX_CHn_BAR_ADDRESS(v)	(v)
+
+/*
+ *  multi-register-define name HW_APBX_CHn_SEMA
+ *              base 0x00000140
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_SEMA(n)	(0x00000140 + (n) * 0x70)
+#define BP_APBX_CHn_SEMA_RSVD2	24
+#define BM_APBX_CHn_SEMA_RSVD2	0xFF000000
+#define BF_APBX_CHn_SEMA_RSVD2(v) \
+		(((v) << 24) & BM_APBX_CHn_SEMA_RSVD2)
+#define BP_APBX_CHn_SEMA_PHORE	16
+#define BM_APBX_CHn_SEMA_PHORE	0x00FF0000
+#define BF_APBX_CHn_SEMA_PHORE(v)  \
+		(((v) << 16) & BM_APBX_CHn_SEMA_PHORE)
+#define BP_APBX_CHn_SEMA_RSVD1	8
+#define BM_APBX_CHn_SEMA_RSVD1	0x0000FF00
+#define BF_APBX_CHn_SEMA_RSVD1(v)  \
+		(((v) << 8) & BM_APBX_CHn_SEMA_RSVD1)
+#define BP_APBX_CHn_SEMA_INCREMENT_SEMA	0
+#define BM_APBX_CHn_SEMA_INCREMENT_SEMA	0x000000FF
+#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)  \
+		(((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA)
+
+/*
+ *  multi-register-define name HW_APBX_CHn_DEBUG1
+ *              base 0x00000150
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_DEBUG1(n)	(0x00000150 + (n) * 0x70)
+#define BM_APBX_CHn_DEBUG1_REQ	0x80000000
+#define BM_APBX_CHn_DEBUG1_BURST	0x40000000
+#define BM_APBX_CHn_DEBUG1_KICK	0x20000000
+#define BM_APBX_CHn_DEBUG1_END	0x10000000
+#define BP_APBX_CHn_DEBUG1_RSVD2	25
+#define BM_APBX_CHn_DEBUG1_RSVD2	0x0E000000
+#define BF_APBX_CHn_DEBUG1_RSVD2(v)  \
+		(((v) << 25) & BM_APBX_CHn_DEBUG1_RSVD2)
+#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID	0x01000000
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY	0x00800000
+#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL	0x00400000
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY	0x00200000
+#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL	0x00100000
+#define BP_APBX_CHn_DEBUG1_RSVD1	5
+#define BM_APBX_CHn_DEBUG1_RSVD1	0x000FFFE0
+#define BF_APBX_CHn_DEBUG1_RSVD1(v)  \
+		(((v) << 5) & BM_APBX_CHn_DEBUG1_RSVD1)
+#define BP_APBX_CHn_DEBUG1_STATEMACHINE	0
+#define BM_APBX_CHn_DEBUG1_STATEMACHINE	0x0000001F
+#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v)  \
+		(((v) << 0) & BM_APBX_CHn_DEBUG1_STATEMACHINE)
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE          0x00
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1      0x01
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3      0x02
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2      0x03
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE   0x04
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT      0x05
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4      0x06
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ       0x07
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH    0x08
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT     0x09
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE         0x0C
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ      0x0D
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN   0x0E
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END      0x15
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT    0x1C
+#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT    0x1E
+
+/*
+ *  multi-register-define name HW_APBX_CHn_DEBUG2
+ *              base 0x00000160
+ *              count 16
+ *              offset 0x70
+ */
+#define HW_APBX_CHn_DEBUG2(n)	(0x00000160 + (n) * 0x70)
+#define BP_APBX_CHn_DEBUG2_APB_BYTES	16
+#define BM_APBX_CHn_DEBUG2_APB_BYTES	0xFFFF0000
+#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) \
+		(((v) << 16) & BM_APBX_CHn_DEBUG2_APB_BYTES)
+#define BP_APBX_CHn_DEBUG2_AHB_BYTES	0
+#define BM_APBX_CHn_DEBUG2_AHB_BYTES	0x0000FFFF
+#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v)  \
+		(((v) << 0) & BM_APBX_CHn_DEBUG2_AHB_BYTES)
+
+#define HW_APBX_VERSION	(0x00000800)
+
+#define BP_APBX_VERSION_MAJOR	24
+#define BM_APBX_VERSION_MAJOR	0xFF000000
+#define BF_APBX_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_APBX_VERSION_MAJOR)
+#define BP_APBX_VERSION_MINOR	16
+#define BM_APBX_VERSION_MINOR	0x00FF0000
+#define BF_APBX_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_APBX_VERSION_MINOR)
+#define BP_APBX_VERSION_STEP	0
+#define BM_APBX_VERSION_STEP	0x0000FFFF
+#define BF_APBX_VERSION_STEP(v)  \
+		(((v) << 0) & BM_APBX_VERSION_STEP)
+#endif /* __ARCH_ARM___APBX_H */
diff --git a/arch/arm/plat-mxs/regs-icoll.h b/arch/arm/plat-mxs/regs-icoll.h
new file mode 100644
index 000000000000..f06ac0d4720b
--- /dev/null
+++ b/arch/arm/plat-mxs/regs-icoll.h
@@ -0,0 +1,293 @@
+/*
+ * Freescale ICOLL Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.50
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___ICOLL_H
+#define __ARCH_ARM___ICOLL_H
+
+#define HW_ICOLL_VECTOR	(0x00000000)
+#define HW_ICOLL_VECTOR_SET	(0x00000004)
+#define HW_ICOLL_VECTOR_CLR	(0x00000008)
+#define HW_ICOLL_VECTOR_TOG	(0x0000000c)
+
+#define BP_ICOLL_VECTOR_IRQVECTOR	2
+#define BM_ICOLL_VECTOR_IRQVECTOR	0xFFFFFFFC
+#define BF_ICOLL_VECTOR_IRQVECTOR(v) \
+		(((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR)
+#define BP_ICOLL_VECTOR_RSRVD1	0
+#define BM_ICOLL_VECTOR_RSRVD1	0x00000003
+#define BF_ICOLL_VECTOR_RSRVD1(v)  \
+		(((v) << 0) & BM_ICOLL_VECTOR_RSRVD1)
+
+#define HW_ICOLL_LEVELACK	(0x00000010)
+
+#define BP_ICOLL_LEVELACK_RSRVD1	4
+#define BM_ICOLL_LEVELACK_RSRVD1	0xFFFFFFF0
+#define BF_ICOLL_LEVELACK_RSRVD1(v) \
+		(((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1)
+#define BP_ICOLL_LEVELACK_IRQLEVELACK	0
+#define BM_ICOLL_LEVELACK_IRQLEVELACK	0x0000000F
+#define BF_ICOLL_LEVELACK_IRQLEVELACK(v)  \
+		(((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK)
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8
+
+#define HW_ICOLL_CTRL	(0x00000020)
+#define HW_ICOLL_CTRL_SET	(0x00000024)
+#define HW_ICOLL_CTRL_CLR	(0x00000028)
+#define HW_ICOLL_CTRL_TOG	(0x0000002c)
+
+#define BM_ICOLL_CTRL_SFTRST	0x80000000
+#define BV_ICOLL_CTRL_SFTRST__RUN      0x0
+#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1
+#define BM_ICOLL_CTRL_CLKGATE	0x40000000
+#define BV_ICOLL_CTRL_CLKGATE__RUN       0x0
+#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1
+#define BP_ICOLL_CTRL_RSRVD3	24
+#define BM_ICOLL_CTRL_RSRVD3	0x3F000000
+#define BF_ICOLL_CTRL_RSRVD3(v)  \
+		(((v) << 24) & BM_ICOLL_CTRL_RSRVD3)
+#define BP_ICOLL_CTRL_VECTOR_PITCH	21
+#define BM_ICOLL_CTRL_VECTOR_PITCH	0x00E00000
+#define BF_ICOLL_CTRL_VECTOR_PITCH(v)  \
+		(((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH)
+#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4         0x1
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8         0x2
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12        0x3
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16        0x4
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20        0x5
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24        0x6
+#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28        0x7
+#define BM_ICOLL_CTRL_BYPASS_FSM	0x00100000
+#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0
+#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1
+#define BM_ICOLL_CTRL_NO_NESTING	0x00080000
+#define BV_ICOLL_CTRL_NO_NESTING__NORMAL  0x0
+#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1
+#define BM_ICOLL_CTRL_ARM_RSE_MODE	0x00040000
+#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE	0x00020000
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE  0x1
+#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE	0x00010000
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0
+#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE  0x1
+#define BP_ICOLL_CTRL_RSRVD1	0
+#define BM_ICOLL_CTRL_RSRVD1	0x0000FFFF
+#define BF_ICOLL_CTRL_RSRVD1(v)  \
+		(((v) << 0) & BM_ICOLL_CTRL_RSRVD1)
+
+#define HW_ICOLL_VBASE	(0x00000040)
+#define HW_ICOLL_VBASE_SET	(0x00000044)
+#define HW_ICOLL_VBASE_CLR	(0x00000048)
+#define HW_ICOLL_VBASE_TOG	(0x0000004c)
+
+#define BP_ICOLL_VBASE_TABLE_ADDRESS	2
+#define BM_ICOLL_VBASE_TABLE_ADDRESS	0xFFFFFFFC
+#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \
+		(((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS)
+#define BP_ICOLL_VBASE_RSRVD1	0
+#define BM_ICOLL_VBASE_RSRVD1	0x00000003
+#define BF_ICOLL_VBASE_RSRVD1(v)  \
+		(((v) << 0) & BM_ICOLL_VBASE_RSRVD1)
+
+#define HW_ICOLL_STAT	(0x00000070)
+
+#define BP_ICOLL_STAT_RSRVD1	7
+#define BM_ICOLL_STAT_RSRVD1	0xFFFFFF80
+#define BF_ICOLL_STAT_RSRVD1(v) \
+		(((v) << 7) & BM_ICOLL_STAT_RSRVD1)
+#define BP_ICOLL_STAT_VECTOR_NUMBER	0
+#define BM_ICOLL_STAT_VECTOR_NUMBER	0x0000007F
+#define BF_ICOLL_STAT_VECTOR_NUMBER(v)  \
+		(((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER)
+
+/*
+ *  multi-register-define name HW_ICOLL_RAWn
+ *              base 0x000000A0
+ *              count 4
+ *              offset 0x10
+ */
+#define HW_ICOLL_RAWn(n)	(0x000000a0 + (n) * 0x10)
+#define HW_ICOLL_RAWn_SET(n)	(0x000000a4 + (n) * 0x10)
+#define HW_ICOLL_RAWn_CLR(n)	(0x000000a8 + (n) * 0x10)
+#define HW_ICOLL_RAWn_TOG(n)	(0x000000ac + (n) * 0x10)
+#define BP_ICOLL_RAWn_RAW_IRQS	0
+#define BM_ICOLL_RAWn_RAW_IRQS	0xFFFFFFFF
+#define BF_ICOLL_RAWn_RAW_IRQS(v)	(v)
+
+/*
+ *  multi-register-define name HW_ICOLL_INTERRUPTn
+ *              base 0x00000120
+ *              count 128
+ *              offset 0x10
+ */
+#define HW_ICOLL_INTERRUPTn(n)	(0x00000120 + (n) * 0x10)
+#define HW_ICOLL_INTERRUPTn_SET(n)	(0x00000124 + (n) * 0x10)
+#define HW_ICOLL_INTERRUPTn_CLR(n)	(0x00000128 + (n) * 0x10)
+#define HW_ICOLL_INTERRUPTn_TOG(n)	(0x0000012c + (n) * 0x10)
+#define BP_ICOLL_INTERRUPTn_RSRVD1	5
+#define BM_ICOLL_INTERRUPTn_RSRVD1	0xFFFFFFE0
+#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \
+		(((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1)
+#define BM_ICOLL_INTERRUPTn_ENFIQ	0x00000010
+#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0
+#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE  0x1
+#define BM_ICOLL_INTERRUPTn_SOFTIRQ	0x00000008
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT    0x0
+#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1
+#define BM_ICOLL_INTERRUPTn_ENABLE	0x00000004
+#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0
+#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE  0x1
+#define BP_ICOLL_INTERRUPTn_PRIORITY	0
+#define BM_ICOLL_INTERRUPTn_PRIORITY	0x00000003
+#define BF_ICOLL_INTERRUPTn_PRIORITY(v)  \
+		(((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY)
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2
+#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3
+
+#define HW_ICOLL_DEBUG	(0x00001120)
+#define HW_ICOLL_DEBUG_SET	(0x00001124)
+#define HW_ICOLL_DEBUG_CLR	(0x00001128)
+#define HW_ICOLL_DEBUG_TOG	(0x0000112c)
+
+#define BP_ICOLL_DEBUG_INSERVICE	28
+#define BM_ICOLL_DEBUG_INSERVICE	0xF0000000
+#define BF_ICOLL_DEBUG_INSERVICE(v) \
+		(((v) << 28) & BM_ICOLL_DEBUG_INSERVICE)
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4
+#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8
+#define BP_ICOLL_DEBUG_LEVEL_REQUESTS	24
+#define BM_ICOLL_DEBUG_LEVEL_REQUESTS	0x0F000000
+#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v)  \
+		(((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS)
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4
+#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8
+#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL	20
+#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL	0x00F00000
+#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v)  \
+		(((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL)
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4
+#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8
+#define BP_ICOLL_DEBUG_RSRVD2	18
+#define BM_ICOLL_DEBUG_RSRVD2	0x000C0000
+#define BF_ICOLL_DEBUG_RSRVD2(v)  \
+		(((v) << 18) & BM_ICOLL_DEBUG_RSRVD2)
+#define BM_ICOLL_DEBUG_FIQ	0x00020000
+#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0
+#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED    0x1
+#define BM_ICOLL_DEBUG_IRQ	0x00010000
+#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0
+#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED    0x1
+#define BP_ICOLL_DEBUG_RSRVD1	10
+#define BM_ICOLL_DEBUG_RSRVD1	0x0000FC00
+#define BF_ICOLL_DEBUG_RSRVD1(v)  \
+		(((v) << 10) & BM_ICOLL_DEBUG_RSRVD1)
+#define BP_ICOLL_DEBUG_VECTOR_FSM	0
+#define BM_ICOLL_DEBUG_VECTOR_FSM	0x000003FF
+#define BF_ICOLL_DEBUG_VECTOR_FSM(v)  \
+		(((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM)
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE         0x000
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1  0x001
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2  0x002
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING      0x004
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3  0x008
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4  0x010
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5  0x100
+#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6  0x200
+
+#define HW_ICOLL_DBGREAD0	(0x00001130)
+#define HW_ICOLL_DBGREAD0_SET	(0x00001134)
+#define HW_ICOLL_DBGREAD0_CLR	(0x00001138)
+#define HW_ICOLL_DBGREAD0_TOG	(0x0000113c)
+
+#define BP_ICOLL_DBGREAD0_VALUE	0
+#define BM_ICOLL_DBGREAD0_VALUE	0xFFFFFFFF
+#define BF_ICOLL_DBGREAD0_VALUE(v)	(v)
+
+#define HW_ICOLL_DBGREAD1	(0x00001140)
+#define HW_ICOLL_DBGREAD1_SET	(0x00001144)
+#define HW_ICOLL_DBGREAD1_CLR	(0x00001148)
+#define HW_ICOLL_DBGREAD1_TOG	(0x0000114c)
+
+#define BP_ICOLL_DBGREAD1_VALUE	0
+#define BM_ICOLL_DBGREAD1_VALUE	0xFFFFFFFF
+#define BF_ICOLL_DBGREAD1_VALUE(v)	(v)
+
+#define HW_ICOLL_DBGFLAG	(0x00001150)
+#define HW_ICOLL_DBGFLAG_SET	(0x00001154)
+#define HW_ICOLL_DBGFLAG_CLR	(0x00001158)
+#define HW_ICOLL_DBGFLAG_TOG	(0x0000115c)
+
+#define BP_ICOLL_DBGFLAG_RSRVD1	16
+#define BM_ICOLL_DBGFLAG_RSRVD1	0xFFFF0000
+#define BF_ICOLL_DBGFLAG_RSRVD1(v) \
+		(((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1)
+#define BP_ICOLL_DBGFLAG_FLAG	0
+#define BM_ICOLL_DBGFLAG_FLAG	0x0000FFFF
+#define BF_ICOLL_DBGFLAG_FLAG(v)  \
+		(((v) << 0) & BM_ICOLL_DBGFLAG_FLAG)
+
+/*
+ *  multi-register-define name HW_ICOLL_DBGREQUESTn
+ *              base 0x00001160
+ *              count 4
+ *              offset 0x10
+ */
+#define HW_ICOLL_DBGREQUESTn(n)	(0x00001160 + (n) * 0x10)
+#define HW_ICOLL_DBGREQUESTn_SET(n)	(0x00001164 + (n) * 0x10)
+#define HW_ICOLL_DBGREQUESTn_CLR(n)	(0x00001168 + (n) * 0x10)
+#define HW_ICOLL_DBGREQUESTn_TOG(n)	(0x0000116c + (n) * 0x10)
+#define BP_ICOLL_DBGREQUESTn_BITS	0
+#define BM_ICOLL_DBGREQUESTn_BITS	0xFFFFFFFF
+#define BF_ICOLL_DBGREQUESTn_BITS(v)	(v)
+
+#define HW_ICOLL_VERSION	(0x000011e0)
+
+#define BP_ICOLL_VERSION_MAJOR	24
+#define BM_ICOLL_VERSION_MAJOR	0xFF000000
+#define BF_ICOLL_VERSION_MAJOR(v) \
+		(((v) << 24) & BM_ICOLL_VERSION_MAJOR)
+#define BP_ICOLL_VERSION_MINOR	16
+#define BM_ICOLL_VERSION_MINOR	0x00FF0000
+#define BF_ICOLL_VERSION_MINOR(v)  \
+		(((v) << 16) & BM_ICOLL_VERSION_MINOR)
+#define BP_ICOLL_VERSION_STEP	0
+#define BM_ICOLL_VERSION_STEP	0x0000FFFF
+#define BF_ICOLL_VERSION_STEP(v)  \
+		(((v) << 0) & BM_ICOLL_VERSION_STEP)
+#endif /* __ARCH_ARM___ICOLL_H */
diff --git a/arch/arm/plat-mxs/timer.c b/arch/arm/plat-mxs/timer.c
new file mode 100644
index 000000000000..7d8f2477f4ba
--- /dev/null
+++ b/arch/arm/plat-mxs/timer.c
@@ -0,0 +1,144 @@
+/*
+ * System timer for Freescale i.MXS
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/device.h>
+#include <mach/regs-timrot.h>
+
+static struct mxs_sys_timer *online_timer;
+
+static irqreturn_t mxs_timer_handler(int irq, void *dev_id);
+
+static cycle_t mxs_get_cycles(struct clocksource *cs)
+{
+	return ~__raw_readl(online_timer->base +
+			    HW_TIMROT_RUNNING_COUNTn(online_timer->id));
+}
+
+static int mxs_set_next_event(unsigned long delta,
+			      struct clock_event_device *dev)
+{
+	unsigned int match;
+	match = __raw_readl(online_timer->base +
+			    HW_TIMROT_MATCH_COUNTn(online_timer->id)) - delta;
+	__raw_writel(match, online_timer->base +
+		     HW_TIMROT_MATCH_COUNTn(online_timer->id));
+	return (int)(match -
+		     __raw_readl(online_timer->base +
+				 HW_TIMROT_RUNNING_COUNTn(online_timer->id)))
+	    > 0 ? -ETIME : 0;
+}
+
+static void mxs_set_mode(enum clock_event_mode mode,
+			 struct clock_event_device *evt)
+{
+}
+
+static struct clock_event_device mxs_clockevent = {
+	.name = "mxs tick timer ",
+	.features = CLOCK_EVT_FEAT_ONESHOT,
+	.shift = 32,
+	.set_next_event = mxs_set_next_event,
+	.set_mode = mxs_set_mode,
+	.rating = 200,
+};
+
+static struct clocksource mxs_clocksource = {
+	.name = "mxs clock source",
+	.rating = 250,
+	.read = mxs_get_cycles,
+	.mask = CLOCKSOURCE_MASK(32),
+	.shift = 10,
+	.flags = CLOCK_SOURCE_IS_CONTINUOUS
+};
+
+static struct irqaction mxs_timer_irq = {
+	.name = "i.MX/mxs Timer Tick",
+	.flags = IRQF_DISABLED | IRQF_TIMER,
+	.handler = mxs_timer_handler,
+	.dev_id = &mxs_clockevent,
+};
+
+static int __init mxs_clocksource_init(struct clk *timer_clk)
+{
+	unsigned int c = clk_get_rate(timer_clk);
+
+	mxs_clocksource.mult = clocksource_hz2mult(c, mxs_clocksource.shift);
+	clocksource_register(&mxs_clocksource);
+	return 0;
+}
+
+static int __init mxs_clockevent_init(struct clk *timer_clk)
+{
+	unsigned int c = clk_get_rate(timer_clk);
+
+	mxs_clockevent.mult = div_sc(c, NSEC_PER_SEC, mxs_clockevent.shift);
+	mxs_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mxs_clockevent);
+	mxs_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFFFFF0,
+							  &mxs_clockevent);
+	mxs_clockevent.cpumask = cpumask_of(0);
+
+	clockevents_register_device(&mxs_clockevent);
+	return 0;
+}
+
+static irqreturn_t mxs_timer_handler(int irq, void *dev_id)
+{
+	struct clock_event_device *c = dev_id;
+	if (__raw_readl(online_timer->base +
+			HW_TIMROT_TIMCTRLn(online_timer->id)) &
+	    BM_TIMROT_TIMCTRLn_IRQ) {
+		__raw_writel(BM_TIMROT_TIMCTRLn_IRQ,
+			     online_timer->base +
+			     HW_TIMROT_TIMCTRLn_CLR(online_timer->id));
+		c->event_handler(c);
+	}
+	return IRQ_HANDLED;
+}
+
+void mxs_timer_init(struct mxs_sys_timer *timer)
+{
+	if (!timer->base || !timer->clk || IS_ERR(timer->clk))
+		return;
+	if (online_timer)
+		return;
+	online_timer = timer;
+	clk_enable(online_timer->clk);
+	__raw_writel(BF_TIMROT_TIMCTRLn_SELECT(online_timer->clk_sel) |
+		     BM_TIMROT_TIMCTRLn_IRQ_EN |
+		     BM_TIMROT_TIMCTRLn_MATCH_MODE,
+		     online_timer->base + HW_TIMROT_TIMCTRLn(online_timer->id));
+	mxs_clocksource_init(online_timer->clk);
+	mxs_clockevent_init(online_timer->clk);
+	setup_irq(online_timer->irq, &mxs_timer_irq);
+}