diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 20:18:36 +0900 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 20:18:36 +0900 |
commit | db3c94a7edc6b29f8d52ba5884dec6a15feeadad (patch) | |
tree | ac9207a44cecafb9104ca4e1f46aecb9fe01383d /arch/arm/plat-s3c24xx/s3c2443-clock.c | |
parent | c9477f38cba225870862fd9e08868ae3d4abdfe0 (diff) | |
parent | 568f0e278c6dd33dc11bd19c4ad781d1f8d86800 (diff) |
Merge branch 'next-samsung-devel' into next-samsung-devel-2
Conflicts:
arch/arm/mach-exynos4/clock.c
arch/arm/mach-s3c2412/gpio.c
arch/arm/mach-s5p64x0/dma.c
arch/arm/mach-s5p64x0/gpiolib.c
Diffstat (limited to 'arch/arm/plat-s3c24xx/s3c2443-clock.c')
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c2443-clock.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 59552c0ea5fb..07a4c81587ac 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -205,9 +205,64 @@ static struct clksrc_clk clksrc_clks[] = { }, }; +static struct clk clk_i2s_ext = { + .name = "i2s-ext", +}; + +/* i2s_eplldiv + * + * This clock is the output from the I2S divisor of ESYSCLK, and is separate + * from the mux that comes after it (cannot merge into one single clock) +*/ + +static struct clksrc_clk clk_i2s_eplldiv = { + .clk = { + .name = "i2s-eplldiv", + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, +}; + +/* i2s-ref + * + * i2s bus reference clock, selectable from external, esysclk or epllref + * + * Note, this used to be two clocks, but was compressed into one. +*/ + +static struct clk *clk_i2s_srclist[] = { + [0] = &clk_i2s_eplldiv.clk, + [1] = &clk_i2s_ext, + [2] = &clk_epllref.clk, + [3] = &clk_epllref.clk, +}; + +static struct clksrc_clk clk_i2s = { + .clk = { + .name = "i2s-if", + .ctrlbit = S3C2443_SCLKCON_I2SCLK, + .enable = s3c2443_clkcon_enable_s, + + }, + .sources = &(struct clksrc_sources) { + .sources = clk_i2s_srclist, + .nr_sources = ARRAY_SIZE(clk_i2s_srclist), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, +}; static struct clk init_clocks_off[] = { { + .name = "iis", + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_IIS, + }, { + .name = "hsspi", + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_HSSPI, + }, { .name = "adc", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, @@ -406,6 +461,8 @@ static struct clk *clks[] __initdata = { }; static struct clksrc_clk *clksrcs[] __initdata = { + &clk_i2s_eplldiv, + &clk_i2s, &clk_usb_bus_host, &clk_epllref, &clk_esysclk, |