diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 12:24:40 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 12:24:40 -0700 |
commit | 4bb2d1009f671815870e8f78e826e4f9071392a7 (patch) | |
tree | 4b9f4e3b349a67d47b11eff7fcebbf57a3c40a1e /arch/arm/plat-s5p | |
parent | ff877c498eb2f9c4ea386270642e383bc867f63c (diff) | |
parent | 83fe628e16d84efc8df2731bc403eae4e4f53801 (diff) |
Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: More SoC support updates" from Olof Johansson:
"This branch contains a handful of updates of SoC base code that had
dependencies on other external trees that have now been merged:
* Support for the new EXYNOS5250 SoC from Samsung
* SMP and power domain support for Tegra3 from NVIDIA
* ux500 updates for exporting SoC information through sysfs"
Fix up trivial merge conflicts as per Olof.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits)
ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer
ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board
ARM: dts: add initial dts file for EXYNOS5250, SMDK5250
ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
ARM: EXYNOS: add support get_core_count() for EXYNOS5250
ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
ARM: EXYNOS: add interrupt definitions for EXYNOS5250
ARM: EXYNOS: add support for EXYNOS5250 SoC
ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
ARM: EXYNOS: add clock part for EXYNOS5250 SoC
ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
ARM: EXYNOS: to declare static for mach-exynos/common.c
ARM: EXYNOS: Add clkdev lookup entry for lcd clock
ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
ARM: tegra: support for secondary cores on Tegra30
ARM: tegra: support for Tegra30 CPU powerdomains
ARM: tegra: add support for Tegra30 powerdomains
ARM: tegra: export tegra_powergate_is_powered()
...
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r-- | arch/arm/plat-s5p/Kconfig | 8 | ||||
-rw-r--r-- | arch/arm/plat-s5p/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/plat-s5p/clock.c | 36 | ||||
-rw-r--r-- | arch/arm/plat-s5p/irq-pm.c | 25 |
4 files changed, 63 insertions, 9 deletions
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 7a308699f816..96bea3202304 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -9,8 +9,8 @@ config PLAT_S5P bool depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) default y - select ARM_VIC if !ARCH_EXYNOS4 - select ARM_GIC if ARCH_EXYNOS4 + select ARM_VIC if !ARCH_EXYNOS + select ARM_GIC if ARCH_EXYNOS select GIC_NON_BANKED if ARCH_EXYNOS4 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB @@ -40,6 +40,10 @@ config S5P_HRT help Use the High Resolution timer support +config S5P_DEV_UART + def_bool y + depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) + config S5P_PM bool help diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 30d8c3016e6b..4bd824136659 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -12,7 +12,6 @@ obj- := # Core files -obj-y += dev-uart.o obj-y += clock.o obj-y += irq.o obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o @@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP) += sleep.o obj-$(CONFIG_S5P_HRT) += s5p-time.o # devices + +obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 963edea7f7e7..f68a9bb11948 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -61,6 +61,20 @@ struct clk clk_fout_apll = { .id = -1, }; +/* BPLL clock output */ + +struct clk clk_fout_bpll = { + .name = "fout_bpll", + .id = -1, +}; + +/* CPLL clock output */ + +struct clk clk_fout_cpll = { + .name = "fout_cpll", + .id = -1, +}; + /* MPLL clock output * No need .ctrlbit, this is always on */ @@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = { .nr_sources = ARRAY_SIZE(clk_src_apll_list), }; +/* Possible clock sources for BPLL Mux */ +static struct clk *clk_src_bpll_list[] = { + [0] = &clk_fin_bpll, + [1] = &clk_fout_bpll, +}; + +struct clksrc_sources clk_src_bpll = { + .sources = clk_src_bpll_list, + .nr_sources = ARRAY_SIZE(clk_src_bpll_list), +}; + +/* Possible clock sources for CPLL Mux */ +static struct clk *clk_src_cpll_list[] = { + [0] = &clk_fin_cpll, + [1] = &clk_fout_cpll, +}; + +struct clksrc_sources clk_src_cpll = { + .sources = clk_src_cpll_list, + .nr_sources = ARRAY_SIZE(clk_src_cpll_list), +}; + /* Possible clock sources for MPLL Mux */ static struct clk *clk_src_mpll_list[] = { [0] = &clk_fin_mpll, diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c index 327acb3a4464..d1bfecae6c9f 100644 --- a/arch/arm/plat-s5p/irq-pm.c +++ b/arch/arm/plat-s5p/irq-pm.c @@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow = 0xffffffffL; int s3c_irq_wake(struct irq_data *data, unsigned int state) { unsigned long irqbit; + unsigned int irq_rtc_tic, irq_rtc_alarm; + +#ifdef CONFIG_ARCH_EXYNOS + if (soc_is_exynos5250()) { + irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC; + irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM; + } else { + irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC; + irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM; + } +#else + irq_rtc_tic = IRQ_RTC_TIC; + irq_rtc_alarm = IRQ_RTC_ALARM; +#endif + + if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) { + irqbit = 1 << (data->irq + 1 - irq_rtc_alarm); - switch (data->irq) { - case IRQ_RTC_TIC: - case IRQ_RTC_ALARM: - irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM); if (!state) s3c_irqwake_intmask |= irqbit; else s3c_irqwake_intmask &= ~irqbit; - break; - default: + } else { return -ENOENT; } + return 0; } |