diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 14:51:38 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-10-20 14:51:38 +0200 |
| commit | 1faca4ced8594d3586302e8d1788a60932f2bbca (patch) | |
| tree | 5130aaa4803a322f3d1f0ff6406f047ed0dba475 /arch/arm/plat-samsung/pwm-clock.c | |
| parent | 112d17d6f75b93e1dcaec2e2232a411148b3bf71 (diff) | |
| parent | 6b6844dd54e4196dd9818bc63b319f93c37a08be (diff) | |
Merge branch 'samsung/devel' of git+ssh://git.linaro.org/home/arndbergmann/public_git/arm-soc into next/devel2
Diffstat (limited to 'arch/arm/plat-samsung/pwm-clock.c')
| -rw-r--r-- | arch/arm/plat-samsung/pwm-clock.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index f1bba88ed2f5..a35ff3bcffe4 100644 --- a/arch/arm/plat-samsung/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c @@ -27,7 +27,7 @@ #include <plat/cpu.h> #include <plat/regs-timer.h> -#include <mach/pwm-clock.h> +#include <plat/pwm-clock.h> /* Each of the timers 0 through 5 go through the following * clock tree, with the inputs depending on the timers. @@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) unsigned long bits; unsigned long shift = S3C2410_TCFG1_SHIFT(id); + unsigned long mux_tclk; + + if (soc_is_s3c24xx()) + mux_tclk = S3C2410_TCFG1_MUX_TCLK; + else if (soc_is_s5p6440() || soc_is_s5p6450()) + mux_tclk = 0; + else + mux_tclk = S3C64XX_TCFG1_MUX_TCLK; + if (parent == s3c24xx_pwmclk_tclk(id)) - bits = S3C_TCFG1_MUX_TCLK << shift; + bits = mux_tclk << shift; else if (parent == s3c24xx_pwmclk_tdiv(id)) bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; else |