diff options
| author | Frank.Li <Frank.Li@freescale.com> | 2009-11-06 01:55:55 -0600 |
|---|---|---|
| committer | Frank.Li <Frank.Li@freescale.com> | 2009-11-06 02:14:35 -0600 |
| commit | 6e8060751ffc741fbeaf3a9882af99895892b021 (patch) | |
| tree | 814e5694d03c32909f1a06f230efcbb3a54ea06d /arch/arm/plat-stmp3xxx | |
| parent | 2b714ca6658f4642a8dad020ac0235499f8f7d54 (diff) | |
ENGR00118047 iMX23 Fix DVFS Can't change frequency and voltage
Policy min and max is set to current frequency.
emi.S use wrong register address
Some line miss at clock.c when port from 28 kernel.
Signed-off-by: Frank.Li <Frank.Li@freescale.com>
Diffstat (limited to 'arch/arm/plat-stmp3xxx')
| -rw-r--r-- | arch/arm/plat-stmp3xxx/clock.c | 17 | ||||
| -rw-r--r-- | arch/arm/plat-stmp3xxx/cpufreq.c | 6 |
2 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c index 68241827821b..dcbabb7eca7e 100644 --- a/arch/arm/plat-stmp3xxx/clock.c +++ b/arch/arm/plat-stmp3xxx/clock.c @@ -3,7 +3,7 @@ * * Author: Vitaly Wool <vital@embeddedalley.com> * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. */ @@ -15,7 +15,6 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -#define DEBUG #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> @@ -359,6 +358,7 @@ static int cpu_set_rate(struct clk *clk, u32 rate) reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); reg_val &= ~0x3F; reg_val |= clkctrl_cpu; + __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); for (i = 10000; i; i--) @@ -531,10 +531,15 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent) hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV); + hbus_val |= 1; + clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; cpu_val |= 1; + __raw_writel(1 << clk->bypass_shift, + clk->bypass_reg + shift); + if (machine_is_stmp378x()) { __raw_writel(hbus_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); @@ -563,10 +568,12 @@ static int clkseq_set_parent(struct clk *clk, struct clk *parent) REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); hclk.rate = 0; } - } -#endif + } else + __raw_writel(1 << clk->bypass_shift, + clk->bypass_reg + shift); +#else __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); - +#endif ret = 0; } diff --git a/arch/arm/plat-stmp3xxx/cpufreq.c b/arch/arm/plat-stmp3xxx/cpufreq.c index 533d1ecd9c8e..89339aea7cc5 100644 --- a/arch/arm/plat-stmp3xxx/cpufreq.c +++ b/arch/arm/plat-stmp3xxx/cpufreq.c @@ -436,8 +436,10 @@ static int __init stmp3xxx_cpu_init(struct cpufreq_policy *policy) pr_debug("got CPU clock rate %d\n", policy->cur); policy->governor = CPUFREQ_DEFAULT_GOVERNOR; - policy->cpuinfo.min_freq = profiles[0].cpu; - policy->cpuinfo.max_freq = profiles[ARRAY_SIZE(profiles) - 1].cpu; + policy->min = policy->cpuinfo.min_freq = profiles[0].cpu; + policy->max = policy->cpuinfo.max_freq = + profiles[ARRAY_SIZE(profiles) - 1].cpu; + policy->cpuinfo.transition_latency = 1000000; /* 1 ms, assumed */ clk_put(cpu_clk); |