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| author | Andre Przywara <andre.przywara@arm.com> | 2018-07-30 13:31:19 +0100 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2018-08-27 15:42:52 +0800 |
| commit | 39defc813264ea87c837900af6f39964353d6b41 (patch) | |
| tree | 5bca4ac8b775212b700637b2679f2a4ddafe082e /arch/arm64/boot/dts/allwinner/Makefile | |
| parent | fcddd1f609ea39dc8377cc587d070e49d32940ff (diff) | |
arm64: dts: allwinner: a64: Add L2 cache nodes
Current kernels complain when booting on an A64 Soc:
....
[ 1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.
Add the L2 cache node and let each CPU point to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/Makefile')
0 files changed, 0 insertions, 0 deletions