diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2018-05-04 02:38:46 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-05-04 17:11:14 +0200 |
| commit | e9a233665464e6cd790d18ea8c7345b4f190321a (patch) | |
| tree | 7683eaa901798d0bf1a259b79d02e12c7a0c0f83 /arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | |
| parent | 1ecefb83ec6415ced08e6d8b9cefa768f3a411a0 (diff) | |
arm64: allwinner: h6: add R_I2C controller
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 2334ba05b12e..c72da8cd9ef5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -204,6 +204,24 @@ #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + + r_i2c_pins: r-i2c { + pins = "PL0", "PL1"; + function = "s_i2c"; + }; + }; + + r_i2c: i2c@7081400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 8>; + resets = <&r_ccu 4>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; |