diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-11-17 15:27:29 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-11-18 13:37:42 +0200 |
| commit | cebef6be66f1654ea64234c07ccc340ac3170f89 (patch) | |
| tree | 74e1637388fcecfeb97324484c727ae4e5ab0652 /arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | |
| parent | eb708b0ff972bfe0e51c38fad6d517fae605ffa8 (diff) | |
arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The
GIC requires shared interrupts to be edge rising or level high. Platform
declares support for both. Set all interrupts type to level high, as this
works fine - tested on Exynos5433-based TM2 board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 796881310bf6..ad71247b074f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -40,9 +40,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <GIC_SPI 0 0>, <GIC_SPI 1 0>, <GIC_SPI 2 0>, - <GIC_SPI 3 0>, <GIC_SPI 4 0>, <GIC_SPI 5 0>, - <GIC_SPI 6 0>, <GIC_SPI 7 0>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; @@ -52,9 +57,14 @@ interrupt-controller; interrupt-parent = <&gic>; - interrupts = <GIC_SPI 8 0>, <GIC_SPI 9 0>, <GIC_SPI 10 0>, - <GIC_SPI 11 0>, <GIC_SPI 12 0>, <GIC_SPI 13 0>, - <GIC_SPI 14 0>, <GIC_SPI 15 0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; }; |