diff options
author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-11-17 09:57:59 +0100 |
---|---|---|
committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-11-18 13:37:56 +0200 |
commit | 4c9eec94a556b11af1ce268d6a25aafbb20f48ce (patch) | |
tree | 4a71ada816f0420303ee99ddd9ce336a79aa0bec /arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | |
parent | e681376e6231321f0930154581f4f8afa3c6b20c (diff) |
arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts
Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos5433-tm2.dts')
-rw-r--r-- | arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 9ea3f32bae9e..3f6d069c8f7e 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -158,6 +158,29 @@ }; }; +&cmu_fsys { + assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, + <&cmu_top CLK_DIV_SCLK_USBDRD30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; + assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, + <66700000>, <66700000>; +}; + &cpu0 { cpu-supply = <&buck3_reg>; }; |