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authorAlim Akhtar <alim.akhtar@samsung.com>2016-04-13 10:12:03 +0530
committerKrzysztof Kozlowski <k.kozlowski@samsung.com>2016-04-13 11:31:44 +0200
commitafa05e55a047f8aa7c865dde5353d96d136aeab2 (patch)
tree47ecf02c1e5a5f4eb6c5d578d781da75ab7e932d /arch/arm64/boot/dts/exynos/exynos7.dtsi
parentfbfcf4bf1c11f16b0afbf77e366cba0c7a621003 (diff)
arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
This patch adds device tree nodes for pdma0 and pdma1 controllers found on exynos7 SoCs. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos7.dtsi')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7.dtsi29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 2450d0a06da5..ca663dfe5189 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -96,6 +96,35 @@
<0x11006000 0x2000>;
};
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma0: pdma@10E10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10E10000 0x1000>;
+ interrupts = <0 225 0>;
+ clocks = <&clock_fsys0 ACLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma1: pdma@10EB0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10EB0000 0x1000>;
+ interrupts = <0 226 0>;
+ clocks = <&clock_fsys0 ACLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
clock_topc: clock-controller@10570000 {
compatible = "samsung,exynos7-clock-topc";
reg = <0x10570000 0x10000>;