diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2016-08-05 09:21:38 +0800 |
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committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:35 +0800 |
commit | 8ff0dafed933d15f63623a3516d9ca56dc0f63b5 (patch) | |
tree | e915c28e466716d8defa0105240faa06d65e1c50 /arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi | |
parent | 754713460d6a2bd5e5f598c55a067f8379a41ffd (diff) |
MLK-13911-2 ARM64: dts: imx8: add arm core common dtsi
Add i.MX8 arm core common dtsi.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi new file mode 100644 index 000000000000..322c7f5ecf11 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8-ca53.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/{ + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 1 clusters having 4 Cortex-A53 cores */ + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; |