diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-08-13 14:20:51 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-11 09:48:23 +0100 |
| commit | ab8af0ac3e9720831197c07de241be1d53e1ebb1 (patch) | |
| tree | 7da81bb8810cc48cb9ea5affbf44b267914e52b8 /arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | |
| parent | db5a2676eed091bfc57135a74986670750d83559 (diff) | |
arm64: dts: fsl: colibri-imx8qxp: add initial device tree
Copied from toradex_imx_4.14.78_1.0.0_ga-bring_up.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index cfd612a76eaf..247f2d568997 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -2388,6 +2388,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2705,6 +2706,118 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; + status = "disabled"; + }; + gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; |