diff options
| author | Han Xu <han.xu@nxp.com> | 2018-10-26 16:29:24 -0500 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:49 +0800 |
| commit | 8a538bd5645343dd7a87bcbaec61c8d11143a8d8 (patch) | |
| tree | 231f04daf4e4f961118dffcfed58fddde6acaea3 /arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts | |
| parent | 4d89ef68ec2fe53a24a399367c493eaeb1a423d7 (diff) | |
MLK-20106: arm64: dts: enable NAND CE1 IOMUX for i.MX8MM
some NAND chips use two CS such as MT29F64G08AFAAA, which require two
enable both CE setting in IOMUX, otherwise the data may write to wrong
pages.
Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts index 52550689964a..1e3459899ded 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts @@ -17,6 +17,7 @@ fsl,pins = < MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 |