diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-05-17 16:46:45 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:52 +0800 |
| commit | 11100c75a85c2202ec49f4a052712bb6e4e27de3 (patch) | |
| tree | a19b8dcb47623902cae2197bd174ea3b325c0312 /arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | |
| parent | 7ee96d85c05b8780b3256aa33a25ab0f9ccba2c3 (diff) | |
MLK-18298-1 ARM64: dts: imx8mm: enable pcie
Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts index 6872eadbcada..544a3b93ed41 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -165,6 +165,14 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x41 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 @@ -718,6 +726,16 @@ }; }; +&pcie0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + status = "okay"; +}; + &uart1 { /* BT */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; |