MLK-18682-5: arm64: dts: imx8mm-evk: define SAI1/5 pll8k and pll11k clks

Specify SAI1/5 pll8k and pll11k clks in order to enable dynamic
reparenting of SAI master clock to the appropriate pll as function of
audio stream rate.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
index 42654f744c4d..7a0d314b86e6 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
@@ -811,6 +811,11 @@
 			<&clk IMX8MM_CLK_SAI1_DIV>;
 	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 	assigned-clock-rates = <0>, <49152000>;
+	clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
+		<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
+		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
+		<&clk IMX8MM_AUDIO_PLL2_OUT>;
+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
 	status = "okay";
 };
 
@@ -831,6 +836,11 @@
 			<&clk IMX8MM_CLK_SAI5_DIV>;
 	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 	assigned-clock-rates = <0>, <49152000>;
+	clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
+		<&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
+		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
+		<&clk IMX8MM_AUDIO_PLL2_OUT>;
+	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
 	fsl,sai-asynchronous;
 	status = "disabled";
 };