diff options
author | Max Krummenacher <max.krummenacher@toradex.com> | 2020-01-15 10:14:34 +0100 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-12 11:06:12 +0100 |
commit | 10b420f3d6162f636a827aea1d356f005c986b7e (patch) | |
tree | 75a1e9dfdb5f1267727122ceec94aa333ceaa6bf /arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi | |
parent | 3a6ede65be9c887781f68de4449b12cece51ea46 (diff) |
arm64: dts: fsl-imx8mm-verdin: eth phy: prevent backfeeding during sleep
Add a 'sleep' pinmuxing which prevents driving RGMII pins and backfeed the
unpowered Ethernet PHY.
When switching the Ethernet PHY supply off, it takes about 400 ms for
the PHY power to go down. So wait a minimum of 500 ms before reenabling
the PHY supply.
Related-to: HAR-2339
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi')
-rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi index 1175dfb56cf5..e83985449d7f 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi @@ -22,6 +22,7 @@ compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + off-on-delay = <500000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_eth>; regulator-boot-on; @@ -192,8 +193,9 @@ phy-handle = <ðphy0>; phy-mode = "rgmii"; phy-supply = <®_ethphy>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; status = "okay"; mdio { @@ -754,6 +756,26 @@ >; }; + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + >; + }; + pinctrl_flexspi0: flexspi0grp { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ |