diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2019-05-27 16:03:31 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2019-05-30 15:51:11 +0800 |
| commit | c47395d23e2384cf5f5c923cb10fdb153ccfb1af (patch) | |
| tree | e009fb08d4289718489527890943544078b31de2 /arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi | |
| parent | 7c1d0c7d51a05089a58d025a4956cc5e7801a923 (diff) | |
MLK-21868-4 ARM64: dts: fsl-imx8mn.dtsi: align the USDHC setting
When setting the usdhc PER clock rate, USDHC1 use the IMX8MN_CLK_USDHC1,
but usdhc3 use the IMX8MN_CLK_USDHC3_ROOT, this is a little bit confuse.
Here align to use IMX8MN_CLK_USDHCx, besides, we can use it directlly
when we want to assign clock parent.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi index babbc35b44c4..6ad46c0b028a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi @@ -764,7 +764,7 @@ <&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; |