diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-05-03 13:13:02 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:24 +0800 |
| commit | 46ac10c8cde91ccedcf9f32cb2c94ac73ea05bc5 (patch) | |
| tree | c4e65b2db53cbee20e7d87e67c0adeb6a81935a4 /arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts | |
| parent | c0ea0ec4dffe7e83f4fdd0dca4719fbe7d9de480 (diff) | |
MLK-18193: arm64: dts: fsl-imx8mq: Fix DCSS clocks for panel use-case
The clocks for DCSS were incorrectly assigned in the rm67191 dts file,
so fix them.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts index 19dbeb41042e..ed8d521708a1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts @@ -33,19 +33,18 @@ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, <&clk IMX8MQ_CLK_DISP_AXI_SRC>, <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, - <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>, <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>, <&clk IMX8MQ_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>, <&clk IMX8MQ_CLK_25M>; assigned-clock-rates = <600000000>, <800000000>, <400000000>, - <400000000>, <0>, + <400000000>, <599999999>; dcss_disp0: port@0 { |