diff options
author | Robert Chiras <robert.chiras@nxp.com> | 2017-11-09 09:38:05 +0200 |
---|---|---|
committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:29:21 +0800 |
commit | 57c94a13500f642e75515440911098e83e7e7744 (patch) | |
tree | 1143d0e80dd74bdd35fd81479f15066063fa4cbd /arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts | |
parent | a403b55810b5fe87eae592862b8b28dcb7b3bd30 (diff) |
MLK-16918-14: arm64: dts: fsl-imx8mq-evk: Enable mipi-dsi with lcdif
Enabled LCDIF-DSI-ADV7535 and LCDIF-DSI-RM67191 paths on MX8MQ EVK
development board.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts new file mode 100644 index 000000000000..90c33bd0761a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts @@ -0,0 +1,113 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/ { + display-subsystem { + status = "disabled"; + }; +}; + +&dcss_drm { + status = "disabled"; +}; + +&hdmi_drm { + status = "disabled"; +}; + +&hdmi_cec { + status = "disabled"; +}; + +&lcdif_drm { + status = "okay"; + + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rate = <120000000>, + <0>, + <599999999>; + + port@0 { + lcdif_mipi_dsi: mipi-dsi-endpoint { + remote-endpoint = <&mipi_dsi_in>; + }; + }; +}; + +&mipi_dsi_phy_drm { + status = "okay"; +}; + +&mipi_dsi_drm { + status = "okay"; + as_bridge; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>, + <&clk IMX8MQ_CLK_DSI_CORE_SRC>, + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_CLK_25M>; + assigned-clock-rates = <24000000>, + <266000000>, + <0>, + <599999999>; + + port@1 { + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; +}; + +&mipi_dsi_bridge_drm { + status = "okay"; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + dsi-lanes = <4>; + panel-width-mm = <68>; + panel-height-mm = <121>; + port { + panel1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge_out>; + }; + }; + }; + + port@1 { + mipi_dsi_bridge_out: endpoint { + remote-endpoint = <&panel1_in>; + }; + }; +}; + +&iomuxc { + imx8mq-evk { + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 + >; + }; + }; +}; |